Seminars, Talks and Other Presentations

Upcoming Seminars 

30/August/2017

 (1:00-2:00 pm)

  514 Rankine Building

The EHBTFET as a suitable low power steep slope switch

Dr. Jose Luis Padilla de la Torre

Abstract: Within the research in bilayer tunneling field-effect transistors (not subjected to the swing limitation of 60mV/dec) exploiting interband tunneling phenomena with tunneling directions aligned with gate induced electric fields, simulation results showed that heterogate configurations for the electron-hole bilayer TFET (HG-EHBTFET) succeeded in suppressing the parasitic tunneling leakage currents appearing as a result of the variable quatization strength inside the channel. In this talk, we show that, for EHBTFETs with intrinsic channels, a new physical limitation arises establishing a minimum attainable value for the tunneling distance at subband alignment only dependent on the body thickness and the material properties. We also analyze the role that the utilization of partially doped channels may entail in the optimization of the EHBTFET through the modulation of tunneling distances and occupancy probabilities.
 

23/August/2017

 (1:00-2:00 pm)

  514 Rankine Building

Vertically Stacked Lateral Si Nanowires Transistors: Solutions for 5nm Technology

Mr. Talib Al-Ameri

 

Abstract: In this work  we  present a simulation study of 5nm vertically stacked lateral nanowires transistor (NWTs). The study is based on calibration of drift-diffusion results against a Poisson- Schrodinger simulations for density-gradient quantum corrections, and against ensemble Monte Carlo simulations to calibrate carrier transport.

Talib.jpeg

16/August/2017

 (1:00-2:00 pm)

  514 Rankine Building

2D Multi-Subband Ensemble Monte Carlo Study of the Tunneling Leakage Mechanisms Impact on Ultrascaled FDSOI, DGSOI and FinFET Devices

Dr. Cristina Medina-Bailon

AbstractThe presence of new physical phenomena affecting the performance of nanometric devices makes unavoidable the fact of including them appropriately in advanced device simulators.  I will present the development of a direct source-to-drain tunneling (S/D tunneling), a gate leakage mechanism (GLM) considering both direct and trap assisted tunneling, and a non-local band-to-band tunneling (BTBT) models on a 2D Multi-Subband Ensemble Monte Carlo simulator.  Then, I will show their simultaneously as well as individually application to study ultra-scaled FDSOI, DGSOI, and FinFET devices.

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09/August/2017

 (1:00-2:00 pm)

  514 Rankine Building

Performance predictions of single-layer In-V double-gate n-and p-type field-effect transistors

Dr. Hamilton Carrillo-Nunez

Abstract: Through ab-initio quantum transport simulations the logic performance of single-layer InAs, InN, InP, and InSb III-V compounds is analyzed in this paper for n- and p-type applications. The key findings are that (i) the low electron effective masses of all these materials lead to very similar and attractive ON-currents in n-type transistors, but cause a rapid deterioration of their sub-threshold swing as the gate length shrinks to 10 nm and below, (ii) the p-type devices show much smaller and scattered current values that are too low to eventually challenge Si FinFETs, and (iii) the density-of-states bottleneck effect strongly influences the behavior of the n-type devices.

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12/April/2017

 (12:30-1:30 pm)

  514 Rankine Building

 Z2FET Compact Modelling 

 Dr. Joris Locord

Research Engineer

Leti, Université de Grenoble

Joris 

     12/April/2017

 (9:30-10:30 am)

 514 Rankine Building

  Thorough Understanding on Z2FET device: Essential Working Mechanism and Further Works to do  

 Prof. Sorin Cristoloveanu 

 Fellow of IEEE, a Fellow of the Electrochemical Society, a Distinguished Lecturer of the Electron Device Society, and Editor of Solid-State Electronics.

 

 Sorin

27/March/2017

 (1:00-2:00 pm)

816 Rankine Building

Designs of Advanced Quantum Information Systems with Si:P alloy

 

Hoon Ryu, Ph.D.

Principal Researcher / Korea Institute of Science and Technology Information

AbstractSilicon(Si)-based quantum computing has attracted attention since Si is known to have the extremely log decoherence time that is suitable to conserve quantum information (Qubits). Rapid progress in the scanning tunneling microscope (STM) lithography opened the possibility for designs of the core cell of Si-based quantum computer as well as other novel devices such as ultra-thin interconnectors and extremely shallow junctions etc., by integrating Phosphorus (P) atoms in bulk Si with a 0.5 nm precision. Needs for the corresponding modeling research, therefore, have been also increased to pre-design such systems&devices with consideration of diverse atomistic effects. In this seminar, (1) we brief the core logistics of charge-based quantum computing using single P atoms in Si layers, (2) introduce the recent modeling works for physically realized P quantum dots in bulk Si and (3) highly doped P nanowires in Si that can be used as ultrathin interconnects in read-out circuits. (4) Finally, we introduce our in-house code and address the particular need for simulations coupled to the high-performance computing, to guide designs of scalable Si-based qubit systems that integrate many P donors.

 

20/Jan/2017

 (2:00-3:30 pm)

644 James Watt Building, South

Characterisation of Filamentary and Non-filamentary Resistive Switching Memory (RRAM) 

Prof. Weidong Zhang 

Professor of Nano-electronics at Liverpool John Moores University

 

Abstract: The latest development in Resistive Switching Memory (RRAM) device technology will be reviewed and its future development and application in neuromorphic computing for IoT and in programmable computing will be discussed. The latest results at LJMU will be presented, including the ones published at IEDM 2016 and VLSI Technology Symposium 2016. A novel Random-Telegraph-Noise based characterisation technique has been developed at LJMU, which, for the first time, provides non-destructive evidence to a range of switching and failure mechanisms in state-of-the-arts filamentary and non-filamentary RRAM devices.  

 Prof. WeidongZhang

30/Nov/2016 

 (1:00-2:00 pm)

514 Rankine Building

The non-equilibrium Green's function approach: modeling of electronic and opto-electronic nano-devices"

Prof. Marc Bescond

Research Fellow at CNRS (CR1-HDR)

 

Abstract: For almost two decades, the non-equilibrium Green's function (NEGF) approach has been intensively developed to perform realistic modeling of quantum transport phenomena in nano-structures and devices [1].  After a brief presentation of the NEGF method, the seminar will first address the impact of a single dopant impurity [2,3] and the access region geometry [4] in ultimate silicon nanowire transistors. In the second part, we will show that it is possible to treat electron-photon interactions and to apply this formalism to the modeling and optimization of III-V third generation solar cells [5]. We will discuss in the last section about an alternative treatment of inelastic interactions in NEGF [6] that significantly reduce the computational time.

References: [1] H. Haug and A.-P. Jauho, Quantum Kinetics in Transport and Optics of Semiconductors, Vol. 123 of Springer Series in Solid-State Sciences (Springer, Berlin, New York, 1996). [2] H. Carrillo-Nuñez, M. Bescond, N. Cavassilas, E. Dib, M. Lannoo, J. Appl. Phys., 116164505 (2014).[3] M. Bescond, H. H. Carrillo-Nuñez, S. Berrada, N. Cavassilas and M. Lannoo, Solid State Electron122, 1 (2016).[4] S. Berrada, M. Bescond, N. Cavassilas, L. Raymond and M. Lannoo, Appl. Phys. Lett107, 153508 (2015).[5] N. Cavassilas, C. Gelly, F. Michelini, M. Bescond, IEEE Journal of Photovoltaics5, 1621 (2015). [6] Y. Lee, M. Lannoo, N. Cavassilas, M. Luisier, and M. Bescond, Phys. Rev. B 93, 205411 (2016).

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9/Nov/2016

(1:00-2:00 pm)

514 Rankine Building

Modeling nanoscale devices using the Non-Equilibrium Green's Function formalism.

Dr. Salim BERRADA

 

Abstract: Nanodevices have reached nowadays dimensions that are comparable to the mean free path of charge carriers. Thus, particles in nanodevices experience strong quantum effects such as confinement, tunneling and coherent transport. Consequently, semi-classical methods fail to model accurately nanoscale devices. The aim of this seminar is to show how the Non Equilibrium Green's Function (NEGF) formalism helps to overcome these problems. I will thus present the concepts that underlie this formalism and show how it can be efficiently implemented numerically. Based on my previous work, I will show that this formalism is powerful to gain deep insight into the device operation, optimize its performance and even propose new device concepts.

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2/Nov/2016

(1:00-2:00 pm)

514 Rankine Building

BTI Induced Time Dependent Variability: A New Analysis Method Accounting for Device-Device Variation  and Within-Device Fluctuation.

Dr Meng Duan

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26/Oct/2016

(1:00-2:00 pm)

514 Rankin Building

 

Vertically Stacked Lateral Si Nanowires Transistors: Solutions for 5nm Technology

Mr. Talib Al-Ameri

 

Abstract: In this work  we  present a simulation study of 5nm vertically stacked lateral nanowires transistor (NWTs). The study is based on calibration of drift-diffusion results against a Poisson- Schrodinger simulations for density-gradient quantum corrections, and against ensemble Monte Carlo simulations to calibrate carrier transport.

Talib.jpeg

12/Oct/2016

(1:00-2:00 pm)

514 Rankin Building

A new model to predict Schottky-barrier height of the nano-scaled junctions

Dr. Jaehyun Lee

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25/May/2016,1-2pm

407 Rankine Building

SNM evaluation in 6T-SRAM based on 70 nm technology node of IMEC device and 22nm Intel FinFET

Mr. Razaidi Hussin

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18/May/2016,1-2pm

407 Rankine Building

Calculation for Electronic Materials (Part II)

Dr. Vihar Gerorgiev

Vihar_Georgiev4.jpg

11/May/2016,1-2pm

407 Rankine Building

Nonequilibrium transport in ultra-scaled nanowires 

Mr. Talib Al-Ameri

 Talib.jpeg

4/May/2016,1-2pm

407 Rankine Building

QuantumWise VNL Induction (Part I)

Dr. Toufik Sadi

 

AbstractThis talk demonstrates how to use the QuantumWise package to calculate the electronic and thermal properties of nano-structures and devices, using silicon nanowires as an example.

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27/April/2016,1-2pm

816 Rankine Building

Supercomputing

Dr. Xingsheng Wang

"I will present you my recent study in introduction to supercomputing. Basics include concept descriptions, several parallel computation theorems, the top 500 ranking, the parallel models (memory shared, message passing), potential applications"

xingsheng.jpg

20/April/2016, 1-2pm

514 Rankine Building

Simulation Analysis of the Electro-Thermal Performance of SOI FinFETs

Dr. Liping Wang

Abstract: Self-heating is one of the major concerns for nanoscale semiconductor transistors in terms of performance and reliability.  The 3D electro-thermal simulation methodology will be described and some results for an SOI FinFET example will be presented. 

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13/April/2016, 1-2pm

514 Rankine Building

Response surface mobility model

Dr. Fikru Adamu-Lema

In this seminar we discuss the response surface mobility model (RS) that can be used for advanced TCAD simulation purpose. After discussing briefly about the RS model we present results to demonstrate the practicality of RS and discuss on its applicability in advanced TCAD simulation tools.

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6/April/2016,1-2pm

514 Rankine Building

Transistor Design for 5nm and Beyond

Dr. Vihar Georgiev

"In this seminar, I will present a presentation given by Victor Moroz on ISQED 2016. The presentation covers key design parameters and band structure properties for MOSFET channel material in a wide range of nanowire and FinFETs. Analysis of the transistor’s performance reveal that silicon scales well down at least to 2 nm node and stress and crystal orientation can be use to slow down the electrons. "

 Vihar_Georgiev4.jpg
     

4/Nov/2015,1-3pm

601 Rankine Building

The Wigner Monte Carlo Method for Modelling Charge Transport in Nanoscale devices (**Invited Seminar **)

Prof. Mixi Nedjalkov (TU Wien)

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8/Oct/2015,2-5pm

514 Rankine Building

Ab initio modelling of defects in thin oxide film and at interfaces in nanoelectronics (**Invited Lecture**)

Prof. Alex Shluger (UCL)

"I will describe theoretical methods used to model defects in thin oxide films used as gate oxides in MOSFETs and in novel memory devices. These defects are responsible for reliability of MOSFETs and electroforming in resistive random access memory (RRAM) devices. I will demonstrate how we combine experimental data with theoretical modelling to identify defects responsible for bias temperature instability in HfO2 MOSFETs and electroforming in SiO2 based RRAM."

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31/08/2015,1-2pm

407 Rankine

Rehearsal for SISPAD presentation

Dr. Fikru Adamu-Lema

Rehearsal for NMDC presentation

Dr. Xingsheng Wang (instead of Mr. Talib Al-Ameri)


 

28/08/2015,1-3pm

407 Rankine

Rehearsal for SISPAD presentation

Dr. Xingsheng Wang

Rehearsal for IWCE presentation

Dr. Vihar Georgiev (instead of Dr. Toufik Sadi )

Rehearsal for SISPAD presentation

Dr. Liping Wang

 

26/08/2015,1-2pm

407 Rankine Building

Rehearsal for SISPAD presentation

Dr. Vihar Georgiev

Rehearsal for ESSDERC presentation

Mr. Razaidi Hussin

 

19/08/2015,1-2pm

407 Rankine

Rehearsal for SISPAD presentation

Mr. Razaidi Hussin



 

05/08/2015,1-2PM

407 Rankine Building

Quantum Mechanics in nano CMOS

Prof. Asen Asenov

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29/07/2015,1-2pm

407 Rankine Building

Density Functional Theory (DFT)

Dr. Vihar Georgiev

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18/06/2015,2-5pm

629 Rankine Building

Workshop on Nanowire Transistors (**Invited Seminar**)

Prof. Douglas Paul, Prof. Iain Thayne, Prof. Asen Asenov, and group fellows (University of Glasgow)


 

17/06/2015,3-5pm

514 Rankine Building

Resistance switching and structural changes in thin silicon rich silica (**Invited Seminar**)

Dr. Adnan Mohanic, Mr. Mark Buckwell, Mr. Luca Montesi (UCL)

 

10/06/2015,1-2pm

514 Rankine Building

Investigation of SRAM using BTI-Aware Statistical Compact Models

Miss Jie Ding

Write time is a critical component of memory performance which often defines cycle time. In order to accurately predict SRAM performance it is also important to take temporal degradation effects into account. This work investigates the influence of BTI induced transistor degradation on dynamic write performance of 20nm bulk CMOS SRAM. The circuit simulations are based on comprehensive physical simulation of the ageing process and on very accurate statistical compact model extraction and generation technology. 

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27/05/2015,1-2pm

514 Rankine Building

Ultimate Scaling of Nanowire Transistor

Mr. Talib Al-Ameri

The main focus of this work is to reveal the impact of various shapes of the cross-section such as circular, elliptical, square, and rectangular on the performance of silicon nanowire transistor (NWT). Also this work aims to establish relationship between the device performance and physical parameters of the Si NWT such as silicon dioxide thickness, channel width (diameter) and channel length. Devices with the following channel length are considered 6nm, 8nm, 10nm, 12nm and 14nm. In this work the quantum mechanical nature of the charge distribution of the channel is introduces by self-consistent Poisson-Schrodinger (PS) formalism. 
Talib.jpeg

13/05/2015,1-2pm

107 LT Rankine Building

 

Modelling of Silicon-Based Resistive Switches

Dr. Toufik Sadi

We present an experimentally-calibrated 3D simulator suitable for the study of resistive random-access memory (RRAM) devices. We explore the switching behaviour of silicon-based RRAM structures, whose operation has been successfully demonstrated through experiments performed by our collaborators. The simulator represents a very predictive tool for exploring the little-known physics of Si-rich RRAMs, and providing efficient designs, in terms of performance, variability and reliability, for both devices and highly-packed memory circuits.
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08/05/2015,1-2pm

107 LT Rankine Building

3D Coupled Electro-Thermal Simulations for FinFETs

Dr. Liping Wang

The introduction of FinFETs represents a radical shift in the semiconductor industry. The 3D FinFET architecture excels in the control of short-channel effects and delivers superior scalability. However, in terms of thermal behavior and reliability the FinFET paradigm introduces challenges, focusing the attention on modeling and analysis of self-heating effects in FinFETs. Recently we have developed a 3D electro-thermal simulation module within the framework of the GSS ‘atomistic’ simulator GARAND. In this seminar the simulation methodology will be presented and 3D coupled electro-thermal simulations will be demonstrated on some FinFET examples. 

lpwang.jpg

1/05/2015,1-2pm

816 Rankine Building

Making Sense of Data: the Statistics of Variability and Reliability (Part I)

Dr. Fikru Adamu-Lema

In this seminar, we will look into the basics of data analysis and data presentation. We start by exploring what do we understand about the data, some of the important concepts in data analysis and the basic definitions of the commonly used measures of central tendency (Mean, median, mode) and measures of disspersion (Standard deviations, variance, quartiles) in data analysis and data preparation. Then, we look further into various ways of data visualisation technics mainly for engineering research applications and how one can select a better way of presenting his data. 

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22/04/2015, 1-2pm.

514 Rankine Building

Switching States, Timed Events and the Reliability Module

Dr. Louis Gerrer

The reliability module has been presented, detailing its necessity and the overall structure of the simulation flow. In particular its capabilities in terms of device architecture and modelling approaches are illustrated by several examples and the state vector framework necessity and complexity is introduced. Finally examples of simulation results are presented for RTN and BTI degradations, both in quasi-static and dynamic ways.

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15/04/2015, 1-2pm.

407 Rankine Building

Variability-Aware Compact Modelling Practice

Dr. Xingsheng Wang

As advanced CMOS technologies progress into nanoscale regime, the Design Technology Co-Optimisation (DTCO) becomes required. Variability is one of the challenges to advanced CMOS integration and circuit design. Therefore how to factor the device variability into DTCO tools and practices is a big challenge. We proposed our hierarchical variability-aware compact modelling extraction and generation practices. It enables the accurate modelling of long-range global process variability and short-range local statistical variability for statistical circuit design. 

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8/04/2015, 2-3pm.

223 Rankine Building

Possible collabration research with HK University

Dr. Vihar Georgiev

In this seminar, I will present part of my work and scientific results which I performed during my visit in University of Hong Kong.  The main objective of my visit was to get experience in running DFT and DFTB+ calculations and possible interface with GARAND software. The work was performed in collaborations with  people from Chemistry department of University of Hong Kong and longterm collaboration has been established.

Vihar_Georgiev4.jpg

25/03/2015, 1-2pm.

816 Rankine Building

Device degradation based on NBTI/PBTI in bulk MOSFET in circuit design perspective

Mr. Razaidi Hussin

This work is the final outcome of the european project MODRED project; for which we developed a statistical reliability aware simulation flow from transistor to circuits. A TCAD calibration methodology based on statistical measurement of a 60nm bulk MOSFET is presented. Statistical compact models of fresh and aged transistors are extracted from large ensembles of TCAD statistical simulations . Compact models representing intermediate stages of degradation, not captured in the TCAD simulations, are interpolated using a proprietary compact model generator. Statistical simulation results from a 6T-SRAM cell aging are presented following various aging scenarios for both static noise margin and intrinsic write time.

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11/03/2015, 1-2pm.

514 Rankine Building

Simulation Study of the Impact of Quantum Confinement on the Electrostatically Driven Performance of Nanowire Transistors

Miss Yijiao Wang

In this seminar the impact of quantum confinement on the silicon nanowire transistor (NWT) performance is illustrated. This work is accomplished by the 3D drift-diffusion module coupled with Density Gradient quantum correlation by calibrating to Poisson Schrodinger solution over nanowire cross sections. Different gate lengths, cross-section shapes, spacer thicknesses and doping steepness were considered. We studied the impact of the quantum corrections on the gate capacitance, the mobile charge in the channel, the drain-induced barrier lowering and the sub-threshold slope. We have also estimated the optimal gate length for different NWT design conditions.

YijiaoWang_copy3.jpg

 

========= DMG seminar new season =========

(Coordinator Dr. Xingsheng Wang)

 
22 May 2013
Room 514 (Rankine Building)
1-2 PM

Molecular-Metal-Oxide-nanoelectronics (M-MOS): Achieving the Molecular Limit

Dr. Vihar Georgiev

This work is based on EPSRC funded M-MOS Programme Grant, which provides an exciting opportunity for research in the field of molecular electronics based on hybridnano-materials. Among the aims of this project is to study extensively using 3D simulations the interplay between variability, scalability and reliability of a non-volatile flash-memory cell, in which the charge-storing components constitute of a layer of polyoxometalates molecular clusters (POMs).

Vihar_Georgiev4.jpg
15 May 2013
Room 514 (Rankine Building)
1-2 PM

SRAM Device and Cell Co-Design Considerations in a 14nm SOI FinFET Technology

Dr Binjie Cheng

We report a systematic study on the impact of process and statistical variability on SRAM design in a 14nm SOI FinFET technology node. A comprehensive statistical compact modelling strategy is developed for the early delivery of reliable PDK model, which enables TCAD-based transistor-cell co-design and path finding during the early phase of a technology node.

binjie.jpg
26 September 2012
Room 514 (Rankine Building)
1-2 PM

Impact of random dopant fluctuations on trap-assisted tunnelling in nanoscale MOSFETs

Dr Louis Gerrer

We introduce a novel simulation approach for the analysis of statistical variability in the trap-assisted tunnelling (TAT) gate leakage current in ultra-scaled MOSFETs. It accounts for the stochastic nature of trapping/emission dynamics underlying TAT current, and enables the simulation of TAT in the time domain. We demonstrate that random dopant fluctuations induce significant variability in the TAT gate leakage and investigate the details of its origin. Finally we present TAT current characteristics for different dopants configurations.

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19 September 2012
Room 514 (Rankine Building)
1-2 PM
 

Statistical Variability in Scaled Generations of n-channel UTB-FD-SOI MOSFETs under the Influence of RDF, LER, OTF and MGG 

Dr Stanislav Markov

Statistical variability (SV) critically affects the scaling, performance, leakage power, and reliability of devices, circuits, and systems. The good electrostatic integrity of UTB-FD-SOI transistors tolerates low channel doping and dramatically reduces the statistical variability due to random dopant fluctuations (RDF), but other sources of variability remain pertinent, including line edge roughness (LER), work-function variation (WFV), oxide thickness fluctuations (OTF), and interface trapped charge due to NBTI/PBTI. The different physical nature of these phenomena affects the spread of threshold voltage (VTH), on-current (ION), and drain-induced barrier lowering (DIBL) of the transistors in different ways, and is, for the first time, comprehensively studied here for three low-operational-power(LOP)-technology generations of n-channel UTB-FD-SOI devices with a physical gate length of 22, 16, and 11 nm. 


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12 September 2012
Room 514 (Rankine Building)
1-2 PM

Statistical Variability in 14-nm node SOI FinFETs and its Impact on Corresponding 6T-SRAM Cell Design

Dr. Xingsheng Wang

This paper presents a comprehensive statistical variability study of 14-nm technology node SOI FinFET which is optimized based on extensive exploration of TCAD design space. The variability sources, including random discrete dopants, gate and fin edge roughness, and possible metal gate granularity, are simulated and examined in term of their impacts on device parameters. The impact of intrinsic parameter fluctuations on a high density SOI FinFET 6T-SRAM cell is also investigated. 

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5 September 2012
Room 514 (Rankine Building)
1-2 PM

Comprehensive Statistical Comparison of RTN and BTI in Deeply Scaled MOSFETs by means of 3D ‘Atomistic’ Simulation

Dr Louis Gerrer

We present a thorough statistical investigation of random telegraph noise (RTN) and bias temperature instabilities (BTI) in nanoscale MOSFETs. By means of 3D TCAD ‘atomistic’ simulations, we evaluate the statistical distribution in capture/emission time constants and in threshold voltage shift (ΔVT) amplitudes due to single trapped charge, comparing its impact on RTN and BTI. However, the individual traps in a device cannot be considered as uncorrelated sources of noise because their mutual interaction is fundamental in determining the dispersion of capture/emission time constants in BTI simulation. 

 louis.jpg
29 August 2012
Room 514 (Rankine Building)
1-2 PM

RTS Amplitude Distribution in 20nm SOI FinFETs subject to Statistical Variability

Dr Xingsheng Wang

It presents a comprehensive simulation study of random telegraph signal (RTS) amplitude distributions under the influence of statistical variability in 20nm gate-length, lightly-doped channel FinFETs on an SOI substrate. The distribution of threshold voltage RTS shifts, due to single-charge trapping at the interface, is inherently affected by statistical variability sources including random discrete dopants (RDD), gate- and fin- edge roughness (GER and FER), and metal gate granularity (MGG). The threshold voltage RTS amplitudes in SOI FinFETs deviate from an exponential distribution with a reduced tail, but it increases with increased statistical variability. Moreover, the electrical transfer characteristics due to single charge trapping vary with gate-bias.
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Statistical TCAD Based PDK Development for a FinFET Technology at 14nm Technology node

Dr Binjie Cheng

A TCAD-based process design kit (PDK) development strategy is present for a generic SOI-based FinFET technology targeted at the 14nm technology node. It enables the circuit design exploration and benchmarking at the early technology development stage. Its application for transistor - SRAM cell design and co-optimisation is discussed.

binjie.jpg

22 August 2012
Room 514 (Rankine Building)
1-2 PM

A Unified Computational Scheme for 3D Statistical Simulation of Reliability Degradation of Nanoscale MOSFETs;

Dr. Fikru Adamu-Lema

In this paper we present a comprehensive simulation methodology for oxide reliability degradation considering bias temperature instability, trap assisted tunnelling, and random telegraphic noise in contemporary CMOS transistors. The impact of device variability on capture and emission time-constants, and trap assisted tunnelling are discussed in conjunction with the dispersion in threshold voltage shift due to trapped charge.

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Time Domain Simulation of Statistical Variability and Oxide Degradation Including Trapping/detrapping Dynamics 

Dr. Stanislav Markov

We present a unified modelling framework for the simulation of time-dependent statistical variability resulting from the dynamics of oxide traps. Given that trap dynamics underlie the phenomena of RTN, BTI and TAT leakage, our approach enables the statistical evaluation of reliability parameters. 

stanislav.jpg 
15 August 2012
Room 514 (Rankine Building)
1-2 PM

Simulation of atomic scale effects in nanoelectronic devices

Dr. Vihar Georgiev

In this work we evaluate the performance of  nanometer scale nanowire MOSTETs using a 3D real-space NEGF approach. Two main sources of variability are considered: interface roughness and random dopant fluctuations. The impact on scattering, access resistance and current-voltage characteristics are carefully investigated.
 

Vihar_Georgiev4.jpg
8 August 2012
Room 514 (Rankine Building)
1-2 PM

Molecular electronics and their not-so-molecular aspects

Dr. Stanislav Markov


Evaluation of the viability and variability of a conceptual non-volatile memory cell, based on a layer of polyoxometalate molecules that replaces the poly-Si floating gate in the conventional flash-cell. Consideration of the scaling issues of  an 18nm cell incorporating polyoxometalates; impact of STI on the programming window and short-channel effects. 

 

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29 June 2012
Room 408 Sir Andrew Frame Lecture Hall
1-2 PM

Myths and Realities about Patents

Dr. Demetris Paraskevopoulos (Managing Director, Nif/T, LLC)


This presentation will describe briefly what is Intellectual Property, and what a Patent is and it is not. Contrast will be drawn on which are the elements for a legally successful patent, as well as what makes a patent commercially valuable and what makes it worthless. Measures of patent quality will be discussed. Examples of patent values will be presented. Business approaches to patent monetization will be briefly reviewed. 
 

6 June 2012
Room 514
1-2 PM

Impact of Back-Gate Bias on Statistical Variability in 22nm n-channel UTBB SOI MOSFETs under the Influence of RDF and LER

Yunxiang Yang (IME Peking University, Beijing, China)


Impact of back-gate bias on statistical variability in 22nm n-channel UTBB MOSFET under the influence of RDF and LER are studied. Two substrate concentrations are considered. Results show that positive back-gate bias degrades the LER-induced threshold voltage and DIBL variability. It also increases the absolute standard deviation of saturation on current distribution due to RDF while has little effect on that of LER. Thanks to an enhancement of more than 30% in saturation on-current, the application of positive back-gate bias reduces the normalised on-current variability. Effects of higher substrate concentration include two aspects: suppressing variability and enhancing the sensitivity of variability to back bias.

30 May 2012
Room 514
1-2 PM

Advanced Statistical Compact Model Extraction/Generation Strategies 
for Accurate SPICE Simulation of Stochastic Variability

Plamen Asenov


This paper focuses on stochastic CMOS variability and corresponding 
strategies to capture it accurately in statistical compact models for 
the purposes of accurate and reliable statistical circuit simulation. 
The compact modeling approach presented in this paper utilizes a firm 
understanding of the physical phenomenon underlying device variability 
and is based on comprehensive ‘atomistic’ 3D device simulations. Both 
statistical compact model extraction methodologies and statistical 
compact model generation strategies are discussed. The accuracy of the 
corresponding statistical compact models is benchmarked with respect to 
the results of physical simulation of large ensembles of devices.
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Monte Carlo Simulations of Ge Implant Free Quantum Well FETs – The Role of Substrate and Channel Orientation

Morgan Kah Chan


The introduction of high mobility channel materials in future CMOS beyond the 15nm technology generation appears in the ITRS as an increasingly viable option to maintain or boost performance for aggressively scaled devices, with Ge being a strong candidate for p-channel transistors. The implant free quantum well (IFQW) device architecture is an attractive vehicle for this development as the confinement in the channel alleviates off-state leakage resulting from the small bandgap of the material. Additionally, the performance can be further boosted by the introduction of biaxial and uniaxial strain, and/or by exploitation of alternate substrate and channel orientations.
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16 May 2012
Room 408
1-2 PM

Use Process Variability to Maximize Electrical Yields

Akis Doganis (Technical Director, TSMC)

Today's IC designs are pushing the performance envelope and demand higher electrical Yields and to minimize PVT.
Circuit Design using Optimization to re-design for maximum electrical Yield while minimizing the PVT as well as de-sensitizing the performance to process variations is of utmost importance.

How this can be done and how long will it take to realize such a complex task when a design cycle is limited in few months?
What, when and how much statistical device variability is needed by the designer?
Can the today's EDA tools cope with the massive data for multimillion device chips?
Is any minimum set of data needed to worst case statistical design?
How device statistical models are obtained and when are provided to circuit designer?
Is product design proceeds the process stabilization and how important is the accuracy of device models?


In this talks, as time permits, we will discuss in details, several aspects concerning all the above questions.
The goal will be to have a methodology and framework to design for electrical variability reduction and to maximize electrical performance yields by incorporating the manufacturing variability data into the most critical phases of the design. Explicit Relationship (Models) between Process, Device, Material, Topology, Circuit, Net Parameters and their Variability to Circuit Performance is necessary and needed by the designer.

And as final note "Electrical performance Variability Reduction resulting to maximum electrical yields is a methodology and a philosophy together. You seek for final target instead of allowing for a margin of errors in each process and design step"
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