Oxide Reliability

Reliability and degradation of nanoscale devices

Device reliability and aging in nano-scale MOSFETs is one of the main3d_plot.PNG concerns   within the semiconductor industry. The device performance degradation stems from both as-manufactured oxide defects and wear-out defects generated during the operational lifetime. The former lead to initial statistical variations of electrical characteristics and the latter induce time dependent variability in the device reliability. This variability is exacerbated by the atomistic nature of matter and charges. Therefore in nanoscale devices, variability and reliability cannot be seen as separated concepts: reliability has to be reinterpreted as a time dependent form of variability.

To capture the statistical nature of device reliability, we are developping a comprehensive framework that accommodates the physical kinetics of trapping and detrapping mechanisms in presence of various sources of variability like Random Dopants Fluctuations, Line Edge Roughness and Metal Grain Granularity. This simulation tools allow to model a large range of degradation related processes like Random Telegraphic Noise (RTN), Bias Temperature Instabilities (BTI) and Trap Assisted Tunneling (TAT), fashioning them into the common framework of the charge trapping phenomenology.TAT.PNGRTN_BTI.PNG

Fully integrated in the 3D atomistic device simulator, Garand, our computational scheme addresses reliability  concerns for various device architectures like SOI, FinFET and BULK MOSFETs and is able to assess statistical based reliability predictions using large device ensembles.

People involved in this work

Fikru Adamu-Lema

 

Related Publications

F. Adamu-Lema, X. Wang, S. M. Amoroso, L. Gerrer, C. Millar and A. Asenov, "Comprehensive ’Atomistic’ Simulation of Statistical Variability and Reliability in 14 nm Generation FinFETs," in Proc. 20th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Washington DC, Sept. 9-11, 2015, pp. 157–160.

V. Georgiev, S. M. Amoroso, L. Gerrer, F. Adamu-Lema and A. Aseov, "Interplay between quantum mechanical effects and a discrete trap position in ultra-scaled FinFETs," in Proc. International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2015, Sept. 9-11, 2015, pp. 246–249.

R. Hussin, L. Gerrer, S. Maria Amoroso, L. Wang, P. Weckx, J. Franco, A. Vanderheyden, D. Vanhaeren, N. Horiguchi, B. Kaczer and A. Asenov, "TCAD-based Methodology for Reliability Assessment of nanoscaled MOSFETs," 11th Conference on Ph.D. Research in Microelectronics and Electronics, 2015: University of Glasgow, Scotland, June 29-July 2, 2015.

R. Hussin, L. Gerrer, J. Ding, S. Maria Amaroso, L. Wang, M. Semicic, P. Weckx, J. Franco, A. Vanderheyden, D. Vanhaeren, N. Horiguchi, B. Kaczer and A. Asenov, "Reliability aware Simulation Flow: From TCAD Calibration to Circuit Level Analysis," International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2015: Washington DC, USA, Sept. 9-11, 2015.

F. Adamu-Lema,S. M. Amoroso, S. Markov, L. Gerrer and A. Asenov, "A Unified Computational Scheme for 3D Statistical Simulation of Reliability Degradations of Nanoscale MOSFETs", The International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Denver, USA, September 5-7 2012 [accepted]

 

See the Publications page for more.

Funding and collaborations

 MORDRED_logo.pngThis research program is supported by the MORDRED European collaborative project on modelling of the reliability and degradation of next generation nanoelectronic devices, involving industrial and research partners (IFX, IMECKUL-E, KUL-P, GSS, GU, TUTTUW, UCL).

 MORDRED is a European 7th framework collaborative project focusing on developing multiscale modelling technology, supported by comprehensive experimental characterization techniques, to study the degradation and reliability of next generation Com plimentary-Metal-Oxide-Semiconductor (CMOS) devices. The project  will provide technologists, device engineers and designers in the nano CMOS industry with tools, reference databases and examples of how to produce future devices that are economical, efficient, and meet high performance, reliability and degradation standards. 

 Project web page: http://webhotel2.tut.fi/fys/mordred/