Xingsheng Wang

Welcome to the webpage of Dr Xingsheng Wang.

Xingsheng Wang received the academic training from several disciplines. He obtained the Ph.D. degree in electronics and electrical engineering from University of Glasgow in July of 2010. His Ph.D. study presented a comprehensive bulk MOSFET scaling projection of device design and statistical variability subject to realistic structures starting from 45nm CMOS technology. He was under the supervisions of Prof. Asen Asenov and Dr. Scott Roy with the full support of ORSAS and EPSRC grant. He acquired MPhil degree in mathematics from Tsinghua University with top prize in January 2007 (Erdös number=4). His master research in mathematics covered analysis on fractals under the directions of Prof. Jiaxin Hu. He had B.S. degree in electronic science and technology from Beijing Technology and Business University with top prize in 2004, focusing on signal processing and telecommunication systems.

Dr Wang is currently Research Associate with Device Modelling Group in the School of Engineering at University of Glasgow. The present research interest involves nanoscale MOSFET devices, TCAD and atomistic modeling and numerical simulations, and intrinsic parameter fluctuations due to statistical variability and reliability. The modelling and simulation tools include TCAD suite Sentaurus and the Glasgow 'atomistic' simulator GARAND for process and device simulations, and BSIM4 and BSIM-CMG for compact modelling.

Contact me

School of Engineering, University of Glasgow, Rankine Building, Oakfield Avenue, Glasgow G12 8LT, Scotland UK

Tel: +44 141 330 2964, Email: Xingsheng.Wang@glasgow.ac.uk

Link: http://userweb.eng.gla.ac.uk/xingsheng.wang/

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Research Areas

StressXX-gatelast.pngTCAD design and simulations of nano-CMOS devices

Closely replicating the front-end processes through calibrated models, the TCAD including Sentaurus enables the cost reduction of technology development and explores possible impact of technology barriers and novelties. Experienced in the usage of TCAD tools including process, structure, and device simulations started from the first release of Sentaurus spaning many years, he is trained owning the expertise in the development and design of nanoscale semiconductor devices, and mastering the comprehensive skills in debuging and analyzing results. Through years' researches, the knowledge and skills in developing 45nm and beyond CMOS technologies are obtained. Device scaling and projection based on TCAD design is one of the most important  constributions. The scaling of planar bulk MOSFETs has been well achieved. Currently, the TCAD team is developing the novel transistors, including scaled FD SOI and FinFETs.

Statistical variability and reliabilityCombinedVariability-RDD-LER2cor10-MGG5-No2.png

Statistical variability in device parameters like threshold voltage due to such as random dopants, line edge roughness, and metal gate granularity has already adversely affected techology and circuits, and statistical varaibility will continously grow due to scaling size in transistors. The statistical aspect of reliability due to like random traps at dielectric interface causes additional parameter fluctuations. Since his PhD study,  he  has got immersed in this field. Recent work in several projects deepens the understanding  the statistical variability and reliability by the full-scale 3D simulations and modeling of variability sources. Through carrying out the predictive statistical simulations on current and future technologies transistors, the physical and engineering implications for future technology and circuit development can also be acquired.

Compact models and circuits

Compact models is the bridge between technology and circuits, and our statistical compact modelling approach takes into account the intrinsic parameter fluctuations inherently, giving the natural advantage over those any makeup method. Common practice is carried out using BSIM4 and BSIM-CMG.

Recent grants worked on

2010 - present

ENIAC joint undertaking project: MOdeling and DEsign of Reliable, process variation-aware Nanoelectronic devices, circuits and systems (MODERN)

The influence of process variations is becoming extremely critical for nanoCMOS technology nodes, due to geometric tolerances and manufacturing non-idealities (such as edge or surface roughness, or the fluctuation of the number of doping atoms). As a result, production yields and figures of merit of a circuit such as performance, power, and reliability have become extremely sensitive to uncontrollable statistical process variations. Although some kind of variability has always existed and been taken into account for designing integrated circuits, the largest impact of variability and the greater influence of random or spatial aspects are setting up a completely new challenge. On top of those difficulties, the deficiency of design techniques and EDA methodologies for tackling PVs makes that challenge even more critical.  The objective of the MODERN project is to develop new paradigms in integrated circuit design which will enable the manufacturing of reliable, low cost, low EMI, high-yield complex products using unreliable and variable devices. (quoted from the project website.)

Consortium: Austria, Denmark, France, Greece, Italy, Spain, Switzerland, The Netherlands, United Kingdom

Project website: http://www.eniac-modern.org/

(http://gow.epsrc.ac.uk/ViewGrant.aspx?GrantRef=EP/G04130X/1 )
2006 - 2010

Meeting the challenges of nano-CMOS electronics (nano-CMOS)

(http://gow.epsrc.ac.uk/ViewGrant.aspx?GrantRef=EP/E003125/1)

Publications

2013

  • B. Cheng, X. Wang, A. R. Brown, J. B. Kuang, D. Reid, C. Millar, S. Nassif and A. Asenov, "SRAM Device and Cell Co-Design Considerations in a 14nm SOI FinFET Technology," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Beijing China, May 19-23, 2013, pp. 2339–2342.
  • X. Wang, A. R. Brown, B. Cheng and A. Asenov, "Drain Bias Impact on Statistical Variability and Reliability in 20 nm Bulk CMOS Technology," in Proc. 14th Ultimate Integration on Silicon (ULIS), U.K. Mar. 19-21, 2013, pp. 65–68.
  • X. Wang, F. Adamu-Lema, B. Cheng and A. Asenov, "Geometry, Temperature, and Body Bias Dependence of Statistical Variability in 20-nm Bulk CMOS Technology: A Comprehensive Simulation Analysis," IEEE Trans. Electron Devices, Vol. 60, No. 5, pp. 1547–1554, May 2013.

2012

  • A. Asenov, B. Cheng, A. R. Brown and X. Wang, "Chapter 15 Impact of Statistical Variability on FinFET Technology: From Device, Statistical Compact Modelling to Statistical Circuit Simulation," in Nyquist AD Converters, Sensor Interfaces, and Robustness, A. H. M. van Roermund, A. Baschirotto and M. Steyaert, Eds. New York: Springer, 2012, pp. 281–291.
  • B. Cheng, A. R. Brown, X. Wang and A. Asenov, "Statistical Variability Study of a 10nm Gate Length SOI FinFET Device," in Proc. IEEE Silicon Nanoelectronics Workshop, Honolulu HI USA, June 10-11, 2012, pp. 69–70.
  • B. Cheng, X. Wang, A. R. Brown, C. Millar, A. Asenov, J. B. Kuang and S. Nassif, "Statistical TCAD Based PDK Development for a FinFET Technology at 14nm Technology node," in Proc. 17th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Denver CO USA, Sept. 5-7, 2012, pp. 113–116.
  • A. S. Mohd Zain, S. Markov, B. Cheng, X. Wang and A. Asenov, "Comprehensive Study of the Statistical Variability in a 22nm Fully-Depleted Ultra-Thin-Body SOI MOSFET," EuroSOI 2012 Conference: Jan. 23-25, 2012.
  • X. Wang, G. Roy, O. Saxod, A. Bajolet, A. Juge and A. Asenov, "Simulation Study of Dominant Statistical Variability Sources in 32-nm High-κ/Metal Gate CMOS," IEEE Electron Device Letters, Vol. 33, No. 5, pp. 643–645, May 2012.
  • X. Wang, A. R. Brown, B. Cheng and A. Asenov, "Statistical distribution of RTS amplitudes in 20nm SOI FinFETs," in Proc. IEEE Silicon Nanoelectronics Workshop, Honolulu HI USA, June 10-11, 2012, pp. 77–78.
  • X. Wang, A. R. Brown, B. Cheng and A. Asenov, "RTS Amplitude Distribution in 20nm SOI FinFETs subject to Statistical Variability," in Proc. 17th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Denver CO USA, Sept. 5-7, 2012, pp. 296–299.
  • X. Wang, B. Cheng, A. R. Brown, C. Millar and A. Asenov, "Statistical Variability in 14-nm node SOI FinFETs and its Impact on Corresponding 6T-SRAM Cell Design," in Proc. 42nd European Solid-State Device Research Conference (ESSDERC), Bordeaux France, Sept. 17-21, 2012, pp. 113–116.

2011

  • K. Abid, X. Wang, A. Z. Khokhar, S. Watson, S. Al-Hasani and F. Rahman, "Electrically tuneable spectral responsivity in gated silicon photodiodes," Applied Physics Letters, Vol. 99, No. 23, p. 231104, Dec. 2011.
  • N. Aymerich, A. Asenov, A. R. Brown, R. Canal, B. Cheng, J. Figueras, A. Gonzalez, E. Herrero, S. Markov, M. Miranda, P. Pouyan, T. Ramirez, A. Rubio, I. Vatajelu, X. Vera, X. Wang and P. Zuber, "New Reliability Mechanisms in Memory Design for sub-22nm Technologies," in Proc. IEEE 17th International On-Line Testing Symposium, Athens, Greece, July 13-15, 2011, pp. 111–114.
  • B. Benbakhti, K. Chan, E. Towie, K. Kalna, C. Riddet, X. Wang, G. Eneman, G. Hellings, K. De Meyer, M. Meuris and A. Asenov, "Numerical analysis of the new Implant-Free Quantum-Well CMOS: DualLogic approach," Solid-State Electronics, Vol. 63, No. 1, pp. 14–18, Sept. 2011.
  • B. Cheng, A. R. Brown, X. Wang and A. Asenov, "Statistical Variability Study of Extreme-Scaled SOI FinFet Device," Intel European Research and Innovation Conference: Oct. 12-14, 2011.
  • S. Markov, X. Wang, N. Moezi and A. Asenov, "Drain Current Collapse in Nanoscaled Bulk MOSFETs Due to Random Dopant Compensation in the Source/Drain Extensions," Electron Devices, IEEE Transactions on, Vol. 58, No. 8, pp. 2385–2393, Aug. 2011.
  • A. S. Mohd Zain, B. Cheng, X. Wang and A. Asenov, "Insights on Device Performance of SOI MOSFET with 60 nm and 15 nm BOX Thickness," EuroSOI 2011 Conference: Jan. 17-19, 2011.
  • X. Wang, S. Markov and A. Asenov, "Channel-length dependence of statistical threshold-voltage variability in extremely scaled HKMG MOSFETs," in Proc. 12th Ultimate Integration on Silicon, Cork, Ireland, Mar. 14-16, 2011, pp. 175–178.
  • X. Wang, S. Roy, A. R. Brown and A. Asenov, "Impact of STI on Statistical Variability and Reliability of Decananometer MOSFETs," IEEE Electron Device Letters, Vol. 32, No. 4, pp. 479–481, Apr. 2011.
  • X. Wang, A. R. Brown, N. M. Idris, S. Markov, G. Roy and A. Asenov, "Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study," IEEE Transactions on Electron Devices, Vol. 58, No. 8, pp. 2293–2301, Aug. 2011.
  • X. Wang, A. R. Brown, B. Cheng and A. Asenov, "Statistical Variability and Reliability in Nanoscale FinFETs," in Proc. IEEE International Electron Devices Meeting (IEDM), Washington DC, Dec. 5-7, 2011, pp. 103–106.

2010

  • B. Benbakhti, K. Kalna, X. Wang, B. Cheng and A. Asenov, "Impact of Raised Source/Drain in the In0.53Ga0.47As Channel Implant-Free Quantum-Well Transistor," in Proc. Ultimate Integration on Silicon, U.K, Mar. 2010, pp. 129–132.
  • B. Bindu, B. Cheng, G. Roy, X. Wang, S. Roy and A. Asenov, "Parameter set and data sampling strategy for accurate yet efficient statistical MOSFET compact model extraction," Solid-State Electronics, Vol. 54, No. 3, pp. 307–315, Mar. 2010.
  • A. R. Brown, X. Wang, S. Markov, B. Cheng and A. Asenov, "Simulation of statistical variability in 18 and 13nm bulk MOSFETs," Intel European Research and Innovation Conference: Oct. 12-14, 2010.
  • B. Cheng, D. Dideban, N. Moezi, C. Millar, G. Roy, X. Wang, S. Roy and A. Asenov, "Statistical Variability Compact Modeling Strategies for BSIM4 and PSP," IEEE Design and Test of Computers, Vol. 27, No. 2, pp. 26–35, Mar./Apr. 2010.
  • B. Cheng, D. Dideban, N. Moezi, C. Millar, G. Roy, X. Wang, S. Roy and A. Asenov, "Capturing Intrinsic Parameter Fluctuations using the PSP Compact Model," in Proc. Design, Automation and Test in Europe, Dresden, Germany, Mar. 8-12, 2010, pp. 650–653.
  • D. Dideban, B. Cheng, N. Moezi, X. Wang and A. Asenov, "Evaluation of 35nm MOSFET Capacitance Components in PSP Compact Model," ICEE2010: Isfahan, Iran, May 11-13, 2010.
  • N. A. Kamsani, B. Cheng, C. Millar, N. Moezi, X. Wang, S. Roy and A. Asenov, "Impact of Slew Rate Definition on the Accuracy of nanoCMOS Inverter Timing Simulations," in Proc. Ultimate Integration on Silicon, Glasgow, Scotland, UK, Mar. 17-19, 2010,

2009

  • X. Wang, S. Roy and A. Asenov, "Impact of Strain on the Performance of high-k/metal replacement gate MOSFETs," in Proc. 10th ULIS, Aachen Germany, Mar. 18-20, 2009, pp. 289–292.

2008

  • A. Asenov, S. Roy, A. R. Brown, G. Roy, C. L. Alexander, C. Riddet, C. Millar, B. Cheng, A. Martinez, N. Seoane, D. Reid, M. Faiz. Bukhori, X. Wang and U. Kovac, "Advanced simulation of statistical variability and reliability in nano CMOS transistors," in Proc. IEDM, USA, Dec. 2008, p. 421.
  • B. Bindu, B. Cheng, G. Roy, X. Wang, S. Roy and A. Asenov, "An efficient data sampling strategy for statistical parameter extraction of nano-MOSFETs," IEEE Workshop on Compact Modeling: Sept. 8-8, 2008.
  • X. Wang, B. Cheng, S. Roy and A. Asenov, "Simulation of Strain Enhanced Variability in nMOSFETs," in Proc. Ultimate Integration on Silicon, Udine Italy, Mar. 12-14, 2008, pp. 89–92.
  • X. Wang, S. Roy and A. Asenov, "Impact of Strain on LER Variability in bulk MOSFETs," in Proc. 38th European Solid-State Device Research Conference (ESSDERC), Edinburgh Scotland U.K. Sept. 15-19, 2008, pp. 190–193.
  • X. Wang, S. Roy and A. Asenov, "High Performance MOSFET Scaling Study from Bulk 45 nm Technology Generation," in Proc. 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), Beijing China, Oct. 20-23, 2008, pp. 484–487.