Welcome to the webpage of Talib Al-Ameri.

Talib Al-Ameri received the B.Sc. and M.Sc. degrees from the University of Technology at Baghdad, in 1998 and 2004, respectively. He is currently pursuing the Ph.D. degree with the Device Modelling Group, School of Engineering, University of Glasgow, Glasgow, U.K. He was a Lecturer with Electronics & Electrical Engineering Department Al-Mustansiriyah University, Baghdad, from 2005.

Contact

School of Engineering, University of Glasgow, Rankine Building, Oakfield Avenue, Glasgow G12 8LT, Scotland UK
 +44 7459109824,        Email:  t.ali.1@research.gla.ac.uk  


Seminars 2015/2016



 

Selected Publications

Simulation Study of Vertically Stacked Lateral Si Nanowires Transistors for 5 nm CMOS Applications

 IEEE Journal of the Electron Devices Society 

  Talib Al-Ameri   V. P. Georgiev   F. Adamu-Lema   Asen Asenov

AbstractIn this paper, we present a simulation study of vertically stacked lateral nanowires transistors (NWTs), which may have applications at 5nm CMOS technology. Our simulation approach is based on a collection of simulation techniques to capture the complexity in such ultra-scaled devices. Initially, we used drift-diffusion methodology with activated Poisson-Schrodinger quantum corrections to accurately capture the quantum confinement in the cross-section of the device. Ensemble Monte Carlo simulations are used to accurately evaluate the drive current capturing the complexity of the carrier transport in the NWTs. We compared the current flow in single, double, and triple vertically stacked lateral NWTs with and without contact resistance. The results presented here suggest a consistent link between channel strain and device performance. Furthermore, we propose a device structure for the 5nm CMOS technology node that meets the required industry scaling projection. We also consider the interplay between various sources of statistical variability and reliability in this paper.

Impact of Quantum Confinement on Transport and the Electrostatic Driven Performance of Silicon Nanowire Transistors at the Scaling LimitStudy

Solid-State Electronics, Elsevier

Talib Al-Ameri, V. Georgiev, T. Sadi1, Y. Wang, F. Adamu-Lema, X. Wang, S. Amoroso, E. Towie, A. Brown, A. Asenov

AbstractIn this work, we investigate the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future CMOS applications at the scaling limit. For the purpose of this paper, we created Si NWTs with two channel crystallographic orientations <110> and <100> and six different cross-section profiles. In the first part, we study the impact of quantum corrections on the gate capacitance and mobile charge in the channel. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic performance of the NWTs, is also investigated. The influence of the rotating of the NWTs cross-sectional geometry by 90o on charge distribution in the channel is also studied. We compare the correlation between the charge profile in the channel and cross-sectional dimension for a circular transistor with four different cross-sections diameters: 5nm, 6nm, 7nm and 8nm. In the second part of this paper, we expand the computational study by including different gate lengths for some of the Si NWTs. As a result, we establish a correlation between the mobile charge distribution in the channel and the gate capacitance, drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All calculations are based on a quantum mechanical description of the mobile charge distribution in the channel. This description is based on the solution of the Schrödinger equation in NWT cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions.

Performance of Vertically Stacked Horizontal Si Nanowires Transistors: A 3D Monte Carlo / 2D Poisson Schrodinger Simulation Study

IEEE Nanotechnology Materials and Devices Conference, France

Talib Al-Ameri, Vihar P. Georgiev, Fikru-Adamu Lema, Toufik Sadi, Ewan Towie, Craig Riddet, Craig Alexander, Asen Asenov

Abstract— In this paper, we present a simulation study of 5nm vertically stacked lateral nanowires transistor (NWTs). The study is based on calibration of drift-diffusion results against a Poisson- Schrodinger simulations for density-gradient quantum corrections, and against ensemble Monte Carlo simulations to calibrate carrier transport. As a result of these calibrated results, we have established a link between channel strain and the device performance. Additionally, we have compared the current flow in a single, double and triple vertically stacked lateral NWTs.

Variability-aware simulations of 5 nm vertically stacked lateral Si nanowires transistors

The International Workshop on Computational Nanotechnology, IWCN2017

 Talib Al-Ameri   V. P. Georgiev   F. Adamu-Lema ;  A. Asenov


Position-dependent performance in 5 nm vertically stacked lateral Si nanowires transistors

The International Workshop on Computational Nanotechnology, IWCN2017

 Talib Al-Ameri   V. P. Georgiev   F. Adamu-Lema ;  A. Asenov

 

Impact of strain on the performance of Si nanowires transistors at the scaling limit: A 3D Monte Carlo / 2D Poisson Schrodinger simulation study

IEEE SISPAD 2016, Germany

 Talib Al-Ameri, Vihar P. Georgiev, Fikru-Adamu Lema, Toufik Sadi, Xingsheng Wang, Ewan Towie, Craig Riddet, Craig Alexander, Asen Asenov

In this work, we investigate the correlation between channel strain and device performance in various n-type Si-NWTs. We establish a correlation between strain, gate length and the cross-section dimension of the transistors. For the purpose of this paper, we simulate Si NWTs with a <110> channel orientation, four different ellipsoidal channel cross-sections and five gate lengths: 4nm, 6nm, 8nm, 10nm and 12nm. We have also analyzed the impact of strain on drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All simulations are based on a quantum mechanical description of the mobile charge distribution in the channel obtained from a 2D solution of the Schrödinger equation in multiple cross-sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions. The current transport along the channel is simulated using 3D Monte Carlo (MC) and drift-diffusion (DD) approaches

Vertically Stacked Lateral Si80Ge20 Nanowires Transistors for 5 nm CMOS Applications

2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (ULIS)

 Talib Al-Ameri,  Asen Asenov

In this work, we present a simulation study of Si80Ge20 and Silicon vertically stacked lateral nanowires transistors (NWTs) with the potential application at 5nm CMOS technology node. Our simulation approach is based on careful selection of simulations techniques in order to capture the complexity of such ultra-scaled devices. We have used ensemble Monte Carlo (MC) simulations in order to accurately predict the drive current taking into account the complexity of the carrier transport in the NWTs.  We have used also drift-diffusion (DD) simulations with quantum corrections based on Poisson-Schrodinger solution in order to accurately calibrate the density-gradient based DD quantum corrections.  Finally, we have benchmarked the current in Si80Ge20 NWTs against Si based NWT. 

Influence of quantum confinement effects and device electrostatic driven performance in ultra-scaled SixGe1-x nanowire transistors.

 

In this work, we have investigated the impact of quantum mechanical effects on the device performance of n-type in ultra-scaled SixGe1-x nanowire transistors (NWT) for possible future applications. For the purpose of this paper, we have simulated SixGe1-x NWTs with a different SixGe1-x molar fraction. However, for all devices the cross-sectional area, dimensions and doping profiles are kept constant in order to provide a fair comparison. Our computational experiment includes also wires with five different gate length 6nm, 8nm, 10nm, 12nm and 14nm all simulated with a various SixGe1-x ratio. As a result, we have established a correlation between the mobile charge distribution in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the subthreshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also have been investigated. More importantly, all calculations are based on the quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrödinger equation, which is indeed mandatory for nanowires with such ultra-scale dimensions.

 Simulation Study of the Impact of Quantum Confinement on the Electrostatically Driven Performance of n-type Nanowire Transistors

Y. Wang, T. Al-Ameri, X. Wang, V. P. Georgiev et. al.,  IEEE Transaction on Electron Devices, 2015, 62 (10), 3229 - 3236 

In this paper, we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies. The 3-D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2-D cross sections along the direction of the transport are presented. The simulated NWTs have cross sections and dimensional characteristics representative of the transistors expected at a 7-nm CMOS technology. Different gate lengths, cross-sectional shapes, spacer thicknesses, and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, mobile charge in the channel, drain-induced barrier lowering, and subthreshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also investigated. We have also estimated the optimal gate length for different NWT design conditions.

T Al-Ameri, Y Wang, VP Georgiev, F Adamu-Lema, X Wang, A Asenov, IEEE NMDC 2015, At Alaska, USA, 23-27

In this work, we have investigated the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future applications. For the purpose of this paper, we have simulated Si NWTs with six different cross-section shapes.However, for all devices, the cross-sectional area is kept constant in order to provide a fair comparison. Additionally, we have expanded the computational experiment by including different gate length and gate materials for each of these six Si NWTs. As a result, we have established a correlation between the mobile charge distribution in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the subthreshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also have been investigated. More importantly, all calculations are based on the quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrödinger equation, which is indeed mandatory for nanowires with such ultra-scale dimensions.

Nanowire transistor solutions for 5nm and beyond

  A. Asenov   Y. Wang   B. Cheng   X. Wang   P. Asenov   T. Al-Ameri   V. P. Georgiev

In this paper we present a comprehensive computational study of silicon nanowire transistor (SNT) and a SNM SRAM cell based on advanced design technology co-optimization (DTCO) TCAD tools. Utilizing this methodology, we provide guidelines and solutions for 5 nm and beyond in CMOS technology. At first, drift-diffusion (DD) results are fully calibrated against a Poisson-Schrodinger (PS) solution to calibrate density-gradient quantum corrections, and ensemble Monte Carlo (EMC) simulations to calibrate transport models. The calibrated DD gives us the capability to simulate statistical variability in nanowire transistors of the 5nm node and beyond accurately and efficiently. Various SNT structures are evaluated in terms of device figures of merit, and optimization of SNTs in terms of electrostatics driven performance is carried out. A variability-aware hierarchical compact model approach for SNT is adopted and used for statistical SRAM simulation near the “scaling limit”. The scaling of SNTs beyond the 5 nm is also discussed.

Influence of quantum confinement effects over device performance in circular and elliptical silicon nanowire transistors

 V. Georgiev, Talib Al-Ameri, Y. Wang, L. Gerrer, S. M. Amoroso, Computational Electronics (IWCE), West Lafayette, IN, USA, 1 - 4

Silicon nanowire transistors (NWTs) are considered one of the most promising device architectures for the sub 7-nm CMOS technology. In such ultra-scaled devices the quantum mechanical effects play a significant role that determines device performance. These quantum confinement effects introduce a threshold voltage shift, simultaneously reducing the gate-to-charge capacitance and the charge in the channel available for transport. Hence, in order to accurately describe the device performance in such ultra-scaled transistors, calculations that consider quantum mechanical effect are essential. In this paper, taking into account the quantum confinement effects, we establish a link between different cross-sections of two NWTs and the device performance.

V. Georgiev, Talib M Ali, Euro-TMCSI, Granada, Spain

Comparison Between Bulk and FDSOI POM Flash Cell: A Multiscale Simulation Study

V. P. Georgiev, S. M. Amoroso, T. Ali, L. Vila-Nadal, C. Busche, L Cronin, A. Asenov, IEEE Transaction on Electron Devices, 2014, 62 (2), 680 - 684 

In this brief, we present a multiscale simulation study of a fully depleted silicon-on-insulator (FDSOI) nonvolatile memory cell based on polyoxometalates (POMs) inorganic molecular clusters used as a storage media embedded in the gate dielectric of flash cells. In particular, we focus our discussion on the threshold voltage variability introduced by random discrete dopants (random dopant fluctuation) and by fluctuations in the distribution of the POM molecules in the storage media (POM fluctuation). To highlight the advantages of the FDSOI POM flash cell, we provide a comparison with an equivalent cell based on conventional (BULK) transistors. The presented simulation framework and methodology is transferable to flash cells based on alternative molecules used as a storage media.