Welcome to the webpage of Talib Al-Ameri.

Contact

School of Engineering, University of Glasgow, R308, Rankine Building, Oakfield Avenue, Glasgow G12 8LT, Scotland UK
 +44 7459109824,        Email:  t.ali.1@research.gla.ac.uk  


Seminars 2015/2016



Selected Publications

 

T. Al-Ameri, V. P. Georgiev, F. Adamu-Lema, and A. Asenov, “Simulation Study of Vertically Stacked Lateral Si Nanowires Transistors for 5 nm CMOS Applications,” IEEE J. Electron Devices Soc., vol. PP, no. 99, pp. 1–1, 2017.

T. Al-Ameri, V. P. Georgiev, T. Sadi, Y. Wang, F. Adamu-Lema, X. Wang, S. M. Amoroso, E. Towie, A. Brown, and A. Asenov, “Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit,” Solid. State. Electron., vol. 129, pp. 73–80, Mar. 2017.

T. Al-Ameri, Y. Wang, V. P. Georgiev, F. Adamu-Lema, X. Wang, and A. Asenov, “Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors,” in 2015 IEEE Nanotechnology Materials and Devices Conference (NMDC), 2015, pp. 1–5, USA.

T. Al-Ameri, V. P. Georgiev, F. Adamu-Lema, X. Wang, and A. Asenov, “Influence of quantum confinement effects and device electrostatic driven performance in ultra-scaled SixGe1−x nanowire transistors,” in IEEE 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2016, pp. 234–237, Vienna, Austria.

T. Al-Ameri, V. P. Georgiev, F. A. Lema, T. Sadi, E. Towie, C. Riddet, C. Alexander, and A. Asenov, “Performance of vertically stacked horizontal Si nanowires transistors: A 3D Monte Carlo/2D Poisson Schrodinger simulation study,” in 2016 IEEE Nanotechnology Materials and Devices Conference (NMDC), 2016, pp. 1–2, France.

T. Al-Ameri, V. P. Georgiev, F. Lema, T. Sadi, X. Wang, E. Towie, C. Riddet, C. Alexander, and A. Asenov, “Impact of strain on the performance of Si nanowires transistors at the scaling limit: A 3D Monte Carlo/2D Poisson Schrodinger Simulation study,” in IEEE 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2016, pp. 213–216, Germany.

T. Al-Ameri, V. P. Georgiev, F. Adamu-Lema, A. Asenov, “Variability-aware Simulations of 5 nm Vertically Stacked Lateral Si Nanowires Transistors” in IOP  International Workshop on Computational Nanotechnology  (IWCN), 2017 UK.

T. Al-Ameri, V. P. Georgiev, F. Adamu-Lema, A. Asenov, “Position Dependent Performance in 5 nm Vertically Stacked Lateral Si Nanowires Transistors” in IOP  International Workshop on Computational Nanotechnology  (IWCN), 2017 UK.

T. Al-Ameri, A. Asenov, “Vertically Stacked Lateral Si80Ge20 Nanowires Transistors for 5 nm CMOS Applications” in IEEE 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2017 Athens.

T. Al-Ameri, V. P. Georgiev, F. Lema,  and A. Asenov, “Does Nanowire Transistor Follow the Golden Ratio?: A 3D Monte Carlo/2D Poisson Schrodinger simulation study,” in IEEE 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2017, Japan.

T. Al-Ameri, "Simulation Study of the Statistical Variability in 5 nm Vertically Stacked Lateral Si Nanowire Transistors", in 2017 IEEE Nanotechnology Materials and Devices Conference (NMDC), 2017.

T. Al-Ameri, " Vertically Stacked Lateral Nanowire Transistors: Optimisation for 5nm CMOS Technology", in 2017 IEEE Nanotechnology Materials and Devices Conference (NMDC), 2017.

 Y. Wang, T. Al-Ameri, X. Wang, V. P. Georgiev, E. Towie, S. M. Amoroso, A. R. Brown, B. Cheng, D. Reid, C. Riddet, L. Shifren, S. Sinha, G. Yeric, R. Aitken, X. Liu, J. Kang, and A. Asenov, “Simulation Study of the Impact of Quantum Confinement on the Electrostatically Driven Performance of n-type Nanowire Transistors,” IEEE Trans. Electron Devices, vol. 62, no. 10, pp. 3229–3236, Oct. 2015

A. Asenov, Y. Wang, B. Cheng, X. Wang, P. Asenov, T. Al-Ameri, and V. P. Georgiev, “Nanowire transistor solutions for 5nm and beyond,” in IEEE 2016 17th International Symposium on Quality Electronic Design (ISQED), 2016, no. 1, pp. 269–274, USA.

F. Adamu-Lema, Meng Duan, S. Berrada, J. Lee, T. Al-Ameri, Vihar Georgiev, Asen Asenov, “Modelling and Simulation of Advanced Semiconductor Devices,” in The Electrochemical Society, 2017, no. 26, pp. 1115, USA.

V. P. Georgiev, T. Ali, Y. Wang, L. Gerrer, S. M. Amoroso, and A. Asenov, “Influence of quantum confinement effects over device performance in circular and elliptical silicon nanowire transistors,” in IEEE 2015 International Workshop on Computational Electronics (IWCE), 2015, pp. 1–4, USA.

V. P. Georgiev, S. M. Amoroso, T. M. Ali, L. Vila-Nadal, C. Busche, L. Cronin, and A. Asenov, “Comparison Between Bulk and FDSOI POM Flash Cell: A Multiscale Simulation Study,” IEEE Trans. Electron Devices, vol. 62, no. 2, pp. 680–684, Feb. 2015.

V. P. Georgiev, T. M. Ali, and A. Asenov, “impact of the quantum confinement, channel length and direction on device performance in cylindrical and elliptical Si nanowires,”Euro-TMCSI, theory, Modelling and Computational Methods for Semiconductors, 2015, Granada, Spain.