Area of work
III-V and Germanium IFQW MOSFETs atomistic simulation
III-V and Germanium are very promising alternative materials for the scaling of post CMOS technologies. Especially, using their much more higher mobility in the channel to replace the 40 year fashion silicon channel is particularly interested. Actually, to favorite the carriers mobility, III-V materials such as InGaAs are used in the channel of n-type Implant-Free Quantum Well (nIFQW) MOSFETs, Germanuim is used in the channel of pIFQW devices. Our subject is to simulate these devices for a gate length under 15nm to obtain then improve the transistor performance.
We use our own atomistic TCAD design kit GARAND in this study. The drift diffusion (DD) aproximation has been applied in device designs of IFQW as well as variability and reliability investigations. Currently, we are making effort to improve both n- and p- devices' performance by changing the device design. Now we have already some preliminary results, and we are making effort to optimize the carriers mobility.
Once the optimized template device design has been completed, the associated variability and reliability simualtion will be processed.
IFQW MOSFETs Monte-Carlo simulation
In most of cases, our DD TCAD tool gives very accurate simulation results. But in the state-of-the-art CMOS device simulations, in high drain bias condition for instance, the results of DD atomistic simulation could be less reliable due to the approximated mobility. That's the reason we need our statistical Monte-Carlo (MC) simulator to obtain a more accurate reference of I-V results and carrier velocity models (then inject in mobility ones).
We have already results of 15nm nIFQW, and they are being checked with previously calibirated 20nm device MC simulation results. At the meantime, we are working on the 15 nm pIFQW MOSFET with 2D and 3D simulations and the optimized channel crystal orientation. All these MC results will be accounted the quantum confinement in the channel and give optimization references to the TCAD device design.
Compact model parameter extraction
When atomistic simulations of III-V/Ge IFQW ideal devices design are completed as well as the associated variability and reliability statistical results, their compact model parameter extraction will be processed. So provides accurate compact models with the well calibrated parameter set and the database for a circuit level EDA simulation using 15nm III-V/Ge MOSFETs into post CMOS circuit applications, such as SRAM cells.
Recent grants worked on
Terascale Reliable Adaptive Memory Systems (TRAMS)
Technology projections indicate that future electronic devices will keep shrinking, being faster and consuming less energy per operation. In the next decade, a single chip will be able to perform trillions of operations per second and provide trillions of bytes per second in off-chip bandwidth. This is the so called Terascale Computing era, where terascale performance will be mainstream, available in personal computer, and being the building block of large data centers with petascale computing capabilities. However, these smaller devices will be much more susceptible to faults and its performance will exhibit a significant degree of variability. As a consequence, to unleash these impressive computing capabilities, a major hurdle in terms of reliability has to be overcome. The TRAMS project is the bridge for reliable, energy efficient and cost effective computing in the era of nanoscale challenges and teraflop opportunities.
Project web page: http://trams-project.eu/