Area of work

Modeling of Statitical Variability and Reliability of Nanoscale MOSFTEs and Flash Memories

Dr. Salvatore Maria Amoroso was born August 1st 1983, in Catania (Italy). He received his Bachelor degree (BS) in 2005, and master degree (MS) in 2008, both in Physics Engineering from Politecnico di Milano, Italy. For his first level graduation thesis he worked on X-ray diffraction analysis of InGaAs/GaAs superlattices within the Department of Physics of the Politecnico di Milano (lab Lness, Como, Italy). For his second level graduation thesis he worked on the development of a physics-based model for program/erase transient behaviour of nitride-based flash memories, within the Department of Electrical Engineering of the Politecnico di Milano and within the R&D NVM center of STmicroelectronics (Agrate B.za, Italy). 

In January 2009, he joined the ''Dipartimento di Elettronica ed Informazione'', Politecnico di Milano, as a Ph.D. student in Information Technology. His primary research interests was in the area of microelectronics (innovative semiconductor memories) and his research activity was mainly focused on the modeling of physical phenomena that govern the statistical variability and reliability of ultra-scaled nitride-based non volatile memories (e.g. TANOS, SONOS memories). This subject was developed in collaboration with the R&D Department of the company Micron. As part of the minor research activity he studied the electronic and structural proprieties of amorphous high-k dielectrics by means of Density Functional Theory based Molecular Dynamics.      

He received the Ph.D. Degree in Electronic Engineering from Politecnico di Milano, in March 2012.

From January 2012 he is with the Device Modeling Group of Univiversity of Glasgow working on the advanced simulation of variability and reliability of decananometer MOSFETs and Flash Memories.

Recent grants worked on

2012 -	MORDRED MORDRED is a European 7th framework collaborative project entitled “Modelling of the reliability and degradation of next generation nanoelectronic devices”. The project focuses on developing multiscale modelling technology, supported by comprehensive experimental characterization techniques, to study the degradation and reliability of next generation Complimentary-Metal-Oxide-Semiconductor (CMOS) devices. The project will provide technologists, device engineers and designers in the nano CMOS industry with tools, reference databases and examples of how to produce future devices that are economical, efficient, and meet high performance, reliability and degradation standards.    Web Page: http://webhotel2.tut.fi/fys/mordred/
2010 - 2012	ENIAC - MODERN European Nanoelectronic Initiative Advisory Council Modeling and Design Reliable, Process Variation-Aware Nanoelectric Devices, Circuits and Systems. The objective of the MODERN project is to develop new paradigms in integrated circuit design which will enable the manufacturing of reliable, low cost, low EMI, high-yield complex products using unreliable and variable devices. Specifically, the main goals of the project are: 1. Advanced, yet accurate, models of process variations for nanometer devices, circuits and complex architectures. 2. Effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance. 3. Design methods and tools to mitigate or tolerate the effects of process variations on those quantities applicable at the device, circuit and architectural levels. 4. Validation of the modeling and design methods and tools on a variety of silicon demonstrators. The MODERN Consortium features strong competence and expertise in the field of advanced technologies, with a well-balanced participation between industry and research institutes. Web Page: http://www.eniac-modern.org/#1
2008-2010	GOSSAMER - FP7 GOSSAMER, or “Gigascale Oriented Solid State flAsh Memory for EuRope” is a European project carried out by a consortium of 13 PARTNER and supported by the European Commission through the FP7 PROGRAM.  The GOSSAMER project aims at the development of the technology for very high density Non Volatile Memories for mass storage applications down to the 22 nm technology node. Objectives:To develop the Charge Trapping Technology for very high density Non Volatile Memories for mass storage, targeting the 22 nm technology node. Start date: January 1st, 2008 Duration: 3 years During the last 15 years, ICTs have provided a number of radically new devices / techno-toys that have improved the daily life of the EU citizen: mobile phone, digital camera, MP3 players, PC, PDA, credit cards, video on discs, flat screen, HD TV, fast communications (ADSL) . The need of more and more “memory” is shared by all applications of ICTs such as enhancing life comfort and security, leisure, education, business and improving work productivity. At the moment there seems to be no sign for a slowing down of memory requirements: in spite of the doubling of memory density every 18 months, the diffusion of broadband communication and digital appliances, and the constant demand for better quality of images and sound, is creating an ever increasing need for large memories in a variety of new media. Solid-state memories are the preferred solution for mobile applications. Their main advantages are the use of consolidated technology, the lack of any mechanical,parts, which results in stronger ruggedness, lighter weight, smaller form-factor, better reliability and, above all, lower power dissipation. Web Page: http://www.fp7-gossamer.eu/

Publications

S. M. Amoroso, L. Gerrer, S. Markov, F. Adamu-Lema, A. Asenov, “RTN and BTI in Nanoscale MOSFETs:  A Comprehensive Statistical Simulation Study”, invited in Solid State Electronics, to be published Feb. 2013.

S. M. Amoroso, A. Ghetti, A. Brown, A. Mauri, C. Monzio Compagnoni, A. Asenov, “Impact of Cell Shape on Random Telegraph Noise in Decananometer Flash Memories”, IEEE Transaction on Electron Devices, pp. 2774-2779, 2012.

L. Vendrame, A. Ghetti, A. Benvenuti, G. Roy,  S. M. Amoroso, A. Asenov, A. Erlebach, “Nanoelectronic Device Electrical Simulation including single atom and trap effects: implication and benchmarking on a Non Volatile Memory test case”, NanotechItaly, Venice, Italy, 2012.

S. M. Amoroso, L. Gerrer, S. Markov, F. Adamu-Lema, A. Asenov, “Comprehensive Statistical Comparison of RTN and BTI in Deeply Scaled MOSFETs by means of 3D ’Atomistic’ Simulation”, ESSDERC proceedings, Bordeaux, France, 2012.

S. Markov, L. Gerrer, F. Adamu-Lema, S. M. Amoroso, A. Asenov, “Time Domain Simulation of Statistical Variability and Oxide Degradation Including Trapping/detrapping Dynamics”, SISPAD proceedings Denver (CO), 2012.

F. Adamu-Lema, S. M. Amoroso, S. Markov, L. Gerrer, A. Asenov “A Unified Computational Scheme for 3D Statistical Simulation of Reliability Degradations of Nanoscale MOSFETs”, SISPAD proceedings Denver (CO), 2012.

L. Gerrer, S. Markov, S. M. Amoroso, F. Adamu-Lema, A. Asenov, “Impact of random dopant fluctuations on trap-assisted tunnelling in nanoscale MOSFETs”, ESREF proceedings, Cagliari, Italy, 2012.

S. M. Amoroso, F. Adamu-Lema, S. Markov, L. Gerrer, A. Asenov, “3D Dynamic RTN Simulation of a 25nm MOSFET: The Importance of Variability in Reliability Evaluation of Decananometer Devices”, IWCE proceedings, Madison (WI) U.S.A., 2012.

A. S. Spinelli, C. Monzio Compagnoni, A. Maconi, S. M. Amoroso, A. L. Lacaita, "Quantum-Mechanical Charge Distribution in Cylindrical Gate-All-Around MOS Devices", IEEE Trans. on Electron Devices, 2012.

A. Ghetti, S.M. Amoroso, A. Mauri, C. Monzio Compagnoni (2012). Impact of nonuniform doping on random telegraph noise in Flash memory device IEEE TRANSACTIONS ON ELECTRON DEVICES , (pp. 309- 315), 59;

S. M. Amoroso, C. L. Alexander, S. Markov, G. Roy, and A. Asenov (2011). A Mobility Model Correction for Atomistic Drift-Diffusion Simulation IEEE SISPAD proceedings, (pp.279-282).

 S. M. Amoroso, C. Monzio Compagnoni, A. Mauri, A. Maconi, A. S. Spinelli, A.L. Lacaita (2011). Semi- analytical model for the transient operation of gate-all-around charge-trap memories IEEE TRANSACTIONS ON ELECTRON DEVICES, (pp. 3116- 3123), 58;

 A. Maconi, S.M. Amoroso, C. Monzio Compagnoni, A. Mauri, A. S. Spinelli, A.L. Lacaita (2011). Three- dimensional simulation of charge-trap memory programming - Part II: Variability IEEE TRANSACTIONS ON ELECTRON DEVICES, (pp. 1872- 1878), 58;

 S.M. Amoroso, A. Maconi, A. Mauri, C. Monzio Compagnoni, A. S. Spinelli, A.L. Lacaita (2011). Three- dimensional simulation of charge-trap memory programming - Part I: Average behavior IEEE TRANSACTIONS ON ELECTRON DEVICES, (pp. 1864- 1871), 58;

 A. Ghetti, S.M. Amoroso, A. Mauri, C. Monzio Compagnoni (2011). Doping engineering for random telegraph noise suppression in deca-nanometer Flash memories. (pp. 91- 94). In: International Memory Workshop. 22/05/2011 - 25/05/2011, Monterey, CA - USA,

 A. Mauri, S. M. Amoroso, C. Monzio Compagnoni, A. Maconi, A. S. Spinelli (2011). Comprehensive numerical simulation of threshold-voltage transients in nitride memories SOLID-STATE ELECTRONICS, (pp. 23- 30), 56;

 G. Ghidini, N. Galbiati, E. Mascellino, C. Scozzari, A. Sebastiani, S. Amoroso, C. Monzio Compagnoni, A. S. Spinelli, A. Maconi, R. Piagge, A. Del Vitto, M. Alessandri, I. Baldi, E. Moltrasio, G. Albini, A. Grossi, P. Tessariol, E. Camerlenghi, A. Mauri (2011). Charge retention phenomena in charge transfer silicon nitride: impact of technology and operating conditions JOURNAL OF VACUUM SCIENCE & TECHNOLOGY. B (pp. 01AE01-1- 01AE01-4), 29;

 S. M. Amoroso, A. Maconi, A. Mauri, C. Monzio Compagnoni, E. Greco, E. Camozzi, S. Vigano', P. Tessariol, A. Ghetti, A. Sottocornola Spinelli, A. L. Lacaita (2010). 3D Monte Carlo simulation of the programming dynamics and their statistical variability in nanoscale charge-trap memories. (pp. 540- 543). In: International Electron Devices Meeting. 5/12/2010 - 8/12/2010, San Francisco - CA - USA,

 C. Miccoli, C. Monzio Compagnoni, S. M. Amoroso, A. Spessot, P. Fantini, A. Visconti, A. Sottocornola Spinelli (2010). Impact of neutral threshold-voltage spread and electron-emission statistics on data retention of nanoscale NAND Flash IEEE ELECTRON DEVICE LETTERS, (pp. 1202- 1204), 31;

 S. M. Amoroso, A. Mauri, N. Galbiati, C. Scozzari, E. Mascellino, E. Camozzi, A. Rangoni, T. Ghilardi, A. Grossi, P. Tessariol, C. Monzio Compagnoni, A. Maconi, A. L. Lacaita, A. Sottocornola Spinelli, G. Ghidini (2010). Reliability constraints for TANOS memories due to alumina trapping and leakage. (pp. 966- 969). In: International Reliability Physics Symposium. 02/05/2010 -06/05/2010, Anaheim, CA - USA,

 A. Maconi, C. Monzio Compagnoni, S. M. Amoroso, E. Mascellino, M. Ghidotti, G. Padovini, A. Sottocornola Spinelli, A. L. Lacaita, A. Mauri, G. Ghidini, N. Galbiati, A. Sebastiani, C. Scozzari, E. Greco, E. Camozzi, P. Tessariol (2010). Investigation of the ISPP dynamics and of the programming efficiency of charge-trap memories. (pp. 444- 447). In: European Solid-State Device Research Conference. 13/09/2010 – 17/09/2010, Siviglia, Spagna,

 A. Mauri, C. Monzio Compagnoni, S. M. Amoroso, A. Maconi, A. Ghetti, A. Sottocornola Spinelli, A. L. Lacaita (2010). Comprehensive investigation of statistical effects in nitride memories - Part I: Physics- based modeling IEEE TRANSACTIONS ON ELECTRON DEVICES, (pp. 2116- 2123), 57;

 C. Monzio Compagnoni, A. Mauri, S. M. Amoroso, A. Maconi, E. Greco, A. Sottocornola Spinelli, A. L. Lacaita (2010). Comprehensive investigation of statistical effects in nitride memories - Part II: Scaling analysis and impact on device performance IEEE TRANSACTIONS ON ELECTRON DEVICES, (pp. 2124- 2131), 57;

 C. MONZIO COMPAGNONI, A. MAURI, S. M. AMOROSO, A. MACONI, A. SOTTOCORNOLA SPINELLI (2009). Physical modeling for programming of TANOS memories in the Fowler-Nordheim regime IEEE TRANSACTIONS ON ELECTRON DEVICES, (pp. 2008- 2015), 56;

 C. SCOZZARI,G. ALBINI,M. ALESSANDRI,S. AMOROSO,P. BACCIAGLIA,A. DEL VITTO,G. GHIDINI (2008). Al2O3 optimization for Charge Trap memory application. (pp. 191- 194). In: Ultimate Integration of Silicon - ULIS. 12/3/2008 - 14/3/2008, Udine,

 A. MAURI,C. MONZIO COMPAGNONI,S. AMOROSO,A. MACONI,F. CATTANEO,A. BENVENUTI, A. SOTTOCORNOLA SPINELLI,A. L. LACAITA (2008). A new physics-based model for TANOS memories program/erase. (pp. 555- 558). In: IEDM International Electron Device Meeting. 15/12/2008 -17/12/2008, San Francisco, USA,