Area of work
Gate oxide reliability
The gate oxide is a fundamental part of Metal Oxide Semiconductor structures. Due to continuous downscaling of devices, it is now so thin that tunnelling current are leaking through. Moreover during device’s lifetime, the gate oxide becomes more and more damaged and traps are formed at the oxide / silicon interface but also in the oxide bulk. This results in gate leakage increase through Trap Assisted Tunnelling, which are a reliability key for flash memories and High-K dielectric devices. Additionally trapped charges through Random Telegraph Noise or Bias Temperature Instabilities phenomenon induce threshold voltage shifts in interaction with variability sources such as discrete dopants distribution.
I am implementing a new oxide reliability tool in the in-house atomistic simulator, allowing both static simulations of trapped charges and trapping dynamics. Oxide trap generation due to device aging are also integrated to monitor device reliability with time. Statistical atomistic simulations have been performed on different devices architectures (SOI, FinFet and bulk MOSFets) regarding trapping phenomenon interactions with various sources of variability. In particular trapping induced threshold voltage shifts, due to Random Telegraph Noise andBias Temperature Instabilities phenomenon have been investigated and their interactions with dopants have been demonstrated, as illustrated in the pictures showing current densities (left) and channel potential (right) for two different traps charge configurations.
Research web page: Reliability
Recent grants worked on
| 2011 - |
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