Ewan Towie

Area of work

3D Monte Carlo simulator development - III-V materials

III-V Impant-Free Quantum-Well device in on-state.

The continued scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) for digital applications in microchips into the nanometre scale is incredibly challenging using traditional architectures and materials. The typical silicon bulk MOSFET structure is not expected to meet the requirements as set in the International Roadmap for Semiconductors (ITRS) at sub-20nm technologies. This has resulted in huge interest in different materials and designs of MOSFETs to improve performance and reduce power consumption including III-V materials that are predicted by the ITRS to enter production in the sub?15nm technologies.

We have developed a three dimensional numerical simulation toolset that allows future MOSFET device designs and materials to be evaluated and optimised. In particular, the use of high-mobility channel materials such as InGaAs and Germanium and advanced device architectures including quantum-well and multi-gate designs can be accurately simulated and their performance predicted. We use a 3D Monte Carlo simulator that captures non-equilibrium, quasi-ballistic carrier transport effects which has been extended to allow for simulation of high-mobility channel materials including degeneracy and multi-valley transport.

Completing numerical simulations with Monte Carlo of future high-mobility channel MOSFETs allows industry designers to understand the performance benefits before productions begins, potentially saving costly development time. The MOSFET can be optimised using numerical simulations to achieve the best performance and the impact of reducing the supply voltage to reduce power consumption can be examined. Coupled with the ability to highlight potential pitfalls in a MOSFET design benefits the $300 billion a year semiconductor industry.

Recent grants worked on

2011 -

Terascale Reliable Adaptive Memory Systems (TRAMS)

Technology projections indicate that future electronic devices will keep shrinking, being faster and consuming less energy per operation. In the next decade, a single chip will be able to perform trillions of operations per second and provide trillions of bytes per second in off-chip bandwidth. This is the so called Terascale Computing era, where terascale performance will be mainstream, available in personal computer, and being the building block of large data centers with petascale computing capabilities. However, these smaller devices will be much more susceptible to faults and its performance will exhibit a significant degree of variability. As a consequence, to unleash these impressive computing capabilities, a major hurdle in terms of reliability has to be overcome. The TRAMS project is the bridge for reliable, energy efficient and cost effective computing in the era of nanoscale challenges and teraflop opportunities.

Project web page: http://trams-project.eu/
2011 -

Atomic Scale Simulations of Nanoelectronic Devices

With interest in post-22nm technology node III-V integration in CMOS increasing, my current work involves development of a full 3D Monte Carlo simulator for III-V materials. This new 3D Monte Carlo simulation has the capability for atomistic simulations allowing the various aspects of random variability to be modelled. Alongside the 3D atomistic Monte Carlo simulator, the proprietry 3D atomstic Drift-Diffusion simulator is also being extended to III-V simulations.
2010 - 2011

DUALLOGIC

DUALLOGIC, a top ranked project, is the flagship of CMOS in FP7. The aim is to develop a high mobility dual-channel Front-End of Line technology as an option for (sub)-22 nm high performance logic ICs. Unlike the present day devices which are all made of Si, we propose that the active channel of pMOS and nMOS transistors in future nanoelectronics could be made of different high mobility semiconductor materials.  In particular, we propose that pMOS are made of Ge and nMOS are made of III-V compound semiconductors co-integrated in the same complex engineered substrate.

Project web-page: http://www.ims.demokritos.gr/DUALLOGIC/
2009 - 2010

III-V MOSFETs for Ultimate CMOS

My first post-doctoral position with the Device Modelling Group was focused on 2D Monte Carlo simulation of future generation III-V MOSFET devices for high-performance CMOS integration beyond the 22nm node. Simulations of the III-V devices were completed using a proprietry Monte Carlo simulator developed in-house which included self-consistent Fermi-Dirac statistics and quantum-corrections. Working alongside the Ultrafast System research group at the University of Glasgow, simulations of advanced III-V gate-stacks for CMOS integration have been compared with experimental data.

Publications

2013

  • V. P. Georgiev, E. Towie and A. Asenov, "Impact of Precisely Positioned Dopants on the Performance of an Ultimate Silicon Nanowire Transistor: A Full Three-Dimensional NEGF Simulation Study," IEEE Transactions on Electron Devices, Vol. 60, No. 3, pp. 965–971, Mar. 2013.
  • S.-Y. Liao, E. Towie, D. Balaz, C. Riddet, B. Cheng and A. Asenov, "Impact of the statistical variability on 15nm IIIV and Ge MOSFET based SRAM design," 14th Ultimate Integration on Silicon (ULIS): Coventry, UK, Mar. 19-21, 2013.
  • E. Towie, C. Riddet and A. Asenov, "Monte Carlo Simulation of the Effect of Interface Roughness in Implant-Free Quantum-Well MOSFETs," 14th Ultimate Integration on Silicon (ULIS): Coventry, UK, Mar. 19-21, 2013.

2012

  • E. Towie, S.-Y. Liao, C. Riddet and A. Asenov, "InGaAs Implant-Free Quantum-Well MOSFETs - Performance Evaluation Using 3D Monte Carlo Simulation," Intel European Research and Innovation Conference: Dublin, Ireland, Oct. 3-4, 2012.

2011

  • B. Benbakhti, K. Kalna, K. H. Chan, E. Towie, G. Hellings, G. Eneman, K. De Meyer, M. Meuris and A. Asenov, "Design and analysis of the In0.53Ga0.47As implant-free quantum-well device structure," Microelectronic Engineering, Vol. 88, No. 4, pp. 358–361,
  • B. Benbakhti, K. Chan, E. Towie, K. Kalna, C. Riddet, X. Wang, G. Eneman, G. Hellings, K. De Meyer, M. Meuris and A. Asenov, "Numerical analysis of the new Implant-Free Quantum-Well CMOS: DualLogic approach," Solid-State Electronics, Vol. 63, No. 1, pp. 14–18, Sept. 2011.
  • E. Towie, J. R. Watling and J. R. Barker, "Remotely screened electron-impurity scattering model for nanoscale MOSFETs," Semiconductor Science and Technology, Vol. 26, No. 5, p. 055008, May 2011.
  • E. Towie, K. Chan, B. Benbakhti, C. Riddet and A. Asenov, "Statistical Variability in Implant-Free Quantum-Well MOSFETs with InGaAs and Ge: A comparative 3D simulation study," Intel European Research and Innovation Conference: Oct. 12-14, 2011.
  • E. Towie, K. Chan, C. Riddet and A. Asenov, "High Mobility Channel MOSFETs for CMOS: A Comparative Implant-Free Quantum-Well 3D Statistical Variability Study," European Workshop on Heterostructure Technology: Nov. 7-9, 2011.

2010

  • B. Benbakhti, E. Towie, K. Kalna, G. Heltlings, G. Eneman, K. De Meyer, M. Meuris and A. Asenov, "Monte Carlo Analysis of In0.53Ga0.47As Implant-Free Quantum-Well Device Performance," Silicon Nanoelectronics Workshop: Honolulu, USA, June 13-14, 2010.

2008

  • J. R. Barker, E. Towie and J. R. Watling, Eds., The influence of polarisation and image charges on electron- impurity scattering in high degeneracy, nanometre scale silicon wrap-round gate MOSFETs, 2008, International Symposium on Advanced Nanodevices and Nanotechnology, Waikoloa, Hawaii, USA, Dec. 2-7, 2007.
  • J. R. Barker, E. Towie and J. R. Watling, "The influence of polarisation and image charges on Electron-Impurity Scattering in High Degeneracy, Nanometre Scale Silicon wrap-round gate MOSFETs," Journal of Physics Conferences Series, Vol. 109, p. 012009, 2008.

2007

  • J. R. Barker, E. Towie and J. R. Watling, "Inhomogeneous Electron-Impurity Scattering in High Degeneracy, nanometer Scale Silicon MOSFETs including image charge effects: new models," 12th International Workshop on Computational Electronics: Oct. 8-10, 2007.
  • J. R. Barker, E. Towie and J. R. Watling, Eds., The influence of polarisation and image charges on electron- impurity scattering in high degeneracy, nanometre scale silicon wrap-round gate MOSFETs, 2008, International Symposium on Advanced Nanodevices and Nanotechnology, Waikoloa, Hawaii, USA, Dec. 2-7, 2007.
  • E. Towie, J. R. Barker and J. R. Watling, "Inhomogeneous Electron-Impurity Scattering in High Degeneracy, Nanometre Scale Silicon MOSFETs," Condensed Matter and Materials Physics 2007: University of Leicester, UK, Apr. 12-13, 2007.