Andrew Brown

Area of work

Atomistic simulator development

Potential in a 45nm MOSFETThe Glasgow ‘atomistic’ simulator is a statistical 3D simulator uniquely designed for the investigation of statistical variability introduced by the discreteness of charge and atomicity of matter. In developing the simulator I have added the capabilities to simulate the major sources of statistical variability, including random discrete dopants (RDD), line edge roughness (LER), line width roughness (LWR), oxide thickness variations (OTV) and poly-silicon granularity (PSG) - a capability that is not available in any other simulation tool. As part of the Reality project new sources of variability such as metal gate granularity (MGG) and N/PBTI-induced trapped charge have been added to the repertoire of the simulator.

Simulating statistical variability in a wide range of CMOS transistor architectures is possible, including Bulk MOSFETs, SOI-FET, Double Gate, FinFETs, Flash Memory and Nanowires. As part of the Trams project I have been incorporating the ability to simulate transistors with novel channel and gate stack materials, such as III-V and Ge MOSFETs.

The drift-diffusion atomistic simulations require advanced simulation methods, such as the inclusion of quantum corrections for both electrons and holes using the density gradient approach, essential for the proper resolution of individual dopants in simulations, and for the correct physical modelling of quantum confinement.

Even though fine-grained discretisation is required for variability-aware modelling, efficient numerical techniques make this an extremely efficient simulator running either on a single processor or when using OpenMP parallelism, and allow the generation of statistical ranges of device characteristics.

Recent grants worked on

2010 -

Terascale Reliable Adaptive Memory Systems (TRAMS)

Technology projections indicate that future electronic devices will keep shrinking, being faster and consuming less energy per operation. In the next decade, a single chip will be able to perform trillions of operations per second and provide trillions of bytes per second in off-chip bandwidth. This is the so called Terascale Computing era, where terascale performance will be mainstream, available in personal computer, and being the building block of large data centers with petascale computing capabilities. However, these smaller devices will be much more susceptible to faults and its performance will exhibit a significant degree of variability. As a consequence, to unleash these impressive computing capabilities, a major hurdle in terms of reliability has to be overcome. The TRAMS project is the bridge for reliable, energy efficient and cost effective computing in the era of nanoscale challenges and teraflop opportunities.

Project web page: http://trams-project.eu/
2008 - 2010

Reliable and Variability tolerant System-on-a-chip Design in More-Moore Technologies (Reality)

As miniaturization of the CMOS technology advances designers will have to deal with increased variability and changing performance of devices. Intrinsic variability of devices which begins to be visible in 65nm devices already will become much more significant in smaller technologies. Soon it will not be possible to design systems using current methods and techniques. Scaling beyond the 32 nm technology node brings a number of problems whose impact on design has not been evaluated yet. Random intra-die process variability, reliability degradation mechanisms and their combined impact on the system level parametric quality metrics are becoming prominent issues.

Dealing with these new challenges will require an adaptation of the current design process: a combination of design time and runtime techniques and methods will be needed to guarantee the correct functioning of Systems on Chip (SoC) over the product’s lifetime, despite the fabrication in unreliable nano-scale technologies. 

The objective of this project is to develop design techniques and methods for real-time guaranteed, energy-efficient, robust and self-adaptive SoC’s.

Publications

2013

  • B. Cheng, X. Wang, A. R. Brown, J. B. Kuang, D. Reid, C. Millar, S. Nassif and A. Asenov, "SRAM Device and Cell Co-Design Considerations in a 14nm SOI FinFET Technology," in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Beijing China, May 19-23, 2013, pp. 2339–2342.
  • X. Wang, A. R. Brown, B. Cheng and A. Asenov, "Drain Bias Impact on Statistical Variability and Reliability in 20 nm Bulk CMOS Technology," in Proc. 14th Ultimate Integration on Silicon (ULIS), U.K. Mar. 19-21, 2013, pp. 65–68.

2012

  • A. Asenov, B. Cheng, A. R. Brown and X. Wang, "Chapter 15 Impact of Statistical Variability on FinFET Technology: From Device, Statistical Compact Modelling to Statistical Circuit Simulation," in Nyquist AD Converters, Sensor Interfaces, and Robustness, A. H. M. van Roermund, A. Baschirotto and M. Steyaert, Eds. New York: Springer, 2012, pp. 281–291.
  • B. Cheng, A. R. Brown, X. Wang and A. Asenov, "Statistical Variability Study of a 10nm Gate Length SOI FinFET Device," in Proc. IEEE Silicon Nanoelectronics Workshop, Honolulu HI USA, June 10-11, 2012, pp. 69–70.
  • B. Cheng, X. Wang, A. R. Brown, C. Millar, A. Asenov, J. B. Kuang and S. Nassif, "Statistical TCAD Based PDK Development for a FinFET Technology at 14nm Technology node," in Proc. 17th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Denver CO USA, Sept. 5-7, 2012, pp. 113–116.
  • X. Wang, A. R. Brown, B. Cheng and A. Asenov, "Statistical distribution of RTS amplitudes in 20nm SOI FinFETs," in Proc. IEEE Silicon Nanoelectronics Workshop, Honolulu HI USA, June 10-11, 2012, pp. 77–78.
  • X. Wang, A. R. Brown, B. Cheng and A. Asenov, "RTS Amplitude Distribution in 20nm SOI FinFETs subject to Statistical Variability," in Proc. 17th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Denver CO USA, Sept. 5-7, 2012, pp. 296–299.
  • X. Wang, B. Cheng, A. R. Brown, C. Millar and A. Asenov, "Statistical Variability in 14-nm node SOI FinFETs and its Impact on Corresponding 6T-SRAM Cell Design," in Proc. 42nd European Solid-State Device Research Conference (ESSDERC), Bordeaux France, Sept. 17-21, 2012, pp. 113–116.

2011

  • A. Asenov, A. R. Brown and B. Cheng, "Statistical aspects of NBTI/PBTI and impact on SRAM yield," in Proc. Design, Automation and Test in Europe, Grenoble, France, Mar. 14-18, 2011,
  • N. Aymerich, A. Asenov, A. R. Brown, R. Canal, B. Cheng, J. Figueras, A. Gonzalez, E. Herrero, S. Markov, M. Miranda, P. Pouyan, T. Ramirez, A. Rubio, I. Vatajelu, X. Vera, X. Wang and P. Zuber, "New Reliability Mechanisms in Memory Design for sub-22nm Technologies," in Proc. IEEE 17th International On-Line Testing Symposium, Athens, Greece, July 13-15, 2011, pp. 111–114.
  • R. Canal, A. Rubio, A. Asenov, A. R. Brown, M. Miranda, P. Zuber, A. Gonzalez and X. Vera, "TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies," Procedia Computer Science, Vol. 7, pp. 148–149, 2011.
  • B. Cheng, A. R. Brown, X. Wang and A. Asenov, "Statistical Variability Study of Extreme-Scaled SOI FinFet Device," Intel European Research and Innovation Conference: Oct. 12-14, 2011.
  • B. Cheng, A. R. Brown and A. Asenov, "Impact of NBTI/PBTI on SRAM Stability Degradation," IEEE Electron Device Letters, Vol. 32, No. 6, pp. 740–742, 2011.
  • N. M. Idris, B. Cheng, A. R. Brown, S. Markov and A. Asenov, "Comprehensive Simulation Study of Statistical Variability in 32nm SOI MOSFET," in Proc. 7th Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits, Jan. 17-19, 2011,
  • A. Martinez, A. R. Brown, S. Roy and A. Asenov, "NEGF simulations of a junctionless Si gate-all-around nanowire transistor with discrete dopants," in Proc. Ultimate Integration on Silicon, Cork, Ireland, Mar. 14-16, 2011,
  • A. Martinez, N. Seoane, M. Aldegunde, A. R. Brown and A. Asenov, "The Role of Discrete Dopants in the Statistical Variability of Narrow Gate-All-Around Silicon Nanowire Transistors," IEEE Transactions on Electron Devices, Vol. 58, No. 8, pp. 2209–2217, Aug. 2011.
  • C. Riddet, C. L. Alexander, A. R. Brown, S. Roy and A. Asenov, "Simulation of "Ab Initio" Quantum Confinement Scattering in UTB MOSFETs Using Three-Dimensional Ensemble Monte Carlo," IEEE Transactions on Electron Devices, Vol. 58, No. 3, pp. 600–608, Mar. 2011.
  • X. Wang, S. Roy, A. R. Brown and A. Asenov, "Impact of STI on Statistical Variability and Reliability of Decananometer MOSFETs," IEEE Electron Device Letters, Vol. 32, No. 4, pp. 479–481, Apr. 2011.
  • X. Wang, A. R. Brown, N. M. Idris, S. Markov, G. Roy and A. Asenov, "Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study," IEEE Transactions on Electron Devices, Vol. 58, No. 8, pp. 2293–2301, Aug. 2011.
  • X. Wang, A. R. Brown, B. Cheng and A. Asenov, "Statistical Variability and Reliability in Nanoscale FinFETs," in Proc. IEEE International Electron Devices Meeting (IEDM), Washington DC, Dec. 5-7, 2011, pp. 103–106.

2010

  • A. Asenov, B. Cheng, D. Dideban, U. Kovac, N. Moezi, C. Millar, G. Roy, A. R. Brown and S. Roy, "Modeling and Simulation of Transistor and Circuit Variability and Reliability," Custom Integrated Circuit Conference: San Jose, California, Sept. 19-22, 2010.
  • A. R. Brown, V. Huard and A. Asenov, "Statistical Simulation of Progressive NBTI Degradation in a 45-nm Technology pMOSFET," IEEE Transactions on Electron Devices, Vol. 57, No. 9, pp. 2320–2323, 2010.
  • A. R. Brown, N. M. Idris, J. R. Watling and A. Asenov, "Impact of Metal Gate Granularity on Threshold Voltage Variability: A Full-Scale Three-Dimensional Statistical Simulation Study," IEEE Electron Device Letters, Vol. 31, No. 11, pp. 1199–1201, Nov. 2010.
  • A. R. Brown, J. R. Watling, G. Roy, C. Riddet, C. L. Alexander, U. Kovac, A. Martinez and A. Asenov, "Use of density gradient quantum corrections in the simulation of statistical variability in MOSFETs," Journal of Computational Electronics, Vol. 9, No. 3-4, pp. 187–196, 2010.
  • A. R. Brown, X. Wang, S. Markov, B. Cheng and A. Asenov, "Simulation of statistical variability in 18 and 13nm bulk MOSFETs," Intel European Research and Innovation Conference: Oct. 12-14, 2010.
  • B. Cheng, A. R. Brown, S. Roy and A. Asenov, "PBTI/NBTI-Related Variability in TB-SOI and DG MOSFETs," IEEE Electron Device Letters, Vol. 31, No. 5, pp. 408–410, May 2010.
  • N. M. Idris, A. R. Brown, J. R. Watling and A. Asenov, "Simulation Study of Workfunction Variability in MOSFETs with Polycrystalline Metal Gates," in Proc. Ultimate Integration on Silicon, Glasgow, Scotland, Mar. 18-19, 2010, pp. 165–168.

2009

  • A. Asenov, A. R. Brown, G. Roy, B. Cheng, C. L. Alexander, C. Riddet, U. Kovac, A. Martinez, N. Seoane and S. Roy, "Simulation of statistical variability in nano-CMOS transistors using drift-diffusion, Monte Carlo and non-equilibrium Green’s function techniques," Journal of Computational Electronics, Vol. 8, No. 3-4, pp. 349–373, 2009.
  • A. R. Brown, A. Martinez, N. Seoane and A. Asenov, "Comparison of Density Gradient and NEGF for 3D Simulation of a Nanowire MOSFET," in Proc. Spanish Conference on Electron Devices, Santiago de Compostela, Spain, Feb. 11-13, 2009, pp. 140–143.
  • M. Faiz. Bukhori, A. R. Brown, S. Roy and A. Asenov, "Simulation of statistical aspects of reliability in nano CMOS transistors," in Proc. International Integrated Reliability Workshop, ser. 2009 IIRW Final Report, California, Oct. 18-22, 2009, pp. 82–85.
  • B. Cheng, S. Roy, A. R. Brown, C. Millar and A. Asenov, "Evaluation of statistical variability in 32 and 22 nm technology generation LSTP MOSFETs," Solid-State Electronics, Vol. 53, No. 7, pp. 767–772, July 2009.
  • N. Seoane, A. Martinez, A. R. Brown and A. Asenov, "Study of surface roughness in extremely small Si nanowire MOSFETs using fully-3D NEGFs," in Proc. Spanish Conference on Electron Devices, Santiago de Compostela, Spain, Feb. 11-13, 2009, pp. 180–183.

2008

  • A. Asenov, A. Cathignol, B. Cheng, K. P. McKenna, A. R. Brown, A. L. Shluger, D. Chanemougame, K. Rochereau and G. Ghibaudo, "Origin of the Asymmetry in the Magnitude of the Statistical Variability of n- and p-Channel Poly-Si Gate Bulk MOSFETs," IEEE Electron. Dev. Lett. Vol. 29, No. 8, pp. 913–915, 2008.
  • A. Asenov, S. Roy, A. R. Brown, G. Roy, C. L. Alexander, C. Riddet, C. Millar, B. Cheng, A. Martinez, N. Seoane, D. Reid, M. Faiz. Bukhori, X. Wang and U. Kovac, "Advanced simulation of statistical variability and reliability in nano CMOS transistors," in Proc. IEDM, USA, Dec. 2008, p. 421.
  • A. R. Brown and A. Asenov, "Capacitance fluctuations in bulk MOSFETs due to random discrete dopants," Journal of Computational Electronics, Vol. 7, No. 3, pp. 115–118, 2008.
  • A. Cathignol, B. Cheng, D. Chanemougame, A. R. Brown, K. Rochereau, G. Ghibaudo and A. Asenov, "Quantitative Evaluation of Statistical Variability Sources in a 45 nm Technological Node LP N-MOSFET," IEEE Electron. Dev. Lett. Vol. 29, No. 6, pp. 609–611, 2008.
  • B. Cheng, S. Roy, A. R. Brown, C. Millar and A. Asenov, "Evaluation of intrinsic parameter fluctuations in 45, 32 and 22 nm technology node LP n-MOSFETs," Proc. ESSDERC 2008: Sept. 15-19, 2008.
  • B. Cheng, S. Roy, A. R. Brown, C. Millar and A. Asenov, "Statistical Variations in 32nm Thin-Body SOI Devices and SRAM Cells," Proc. ICSICT 2008: 2008.
  • A. Martinez, M. Bescond, A. R. Brown, J. R. Barker and A. Asenov, "A Full Non-Equillibrium Green Functions Study of an Stray charge in a Nanowire MOS," J. Comp. Elec, 2008.
  • C. Riddet, A. R. Brown, S. Roy and A. Asenov, "Boundary Conditions for Density Gradient Corrections in 3D Monte Carlo Simulations," Journal of Computational Electronics, Vol. 7, No. 3, pp. 231–235, 2008.
  • N. Seoane, A. Martinez, A. R. Brown, J. R. Barker and A. Asenov, "3D NEGF simulation of ‘ab initio’ scattering from discrete dopants in the source and drain of a nanowire transistor," in Proc. Silicon Nanoelectronics Workshop, Honolulu, HI, USA, June 15-16, 2008,

2007

  • A. R. Brown, G. Roy and A. Asenov, "Poly-Si Gate Related Variability in Decananometre MOSFETs with Conventional Architecture," IEEE Trans. Electron Dev. Vol. 54, No. 11, pp. 3056–3063, 2007.
  • A. R. Brown, A. Martinez, M. Bescond and A. Asenov, "Nanowire MOSFET variability: a 3D density gradient versus NEGF approach," in Proc. Silicon Nanoelectronics Workshop, Kyoto, Japan, June 10-11, 2007, pp. 127–128.
  • T. D. Drysdale, A. R. Brown, G. Roy, S. Roy and A. Asenov, "Interconnect variability within standard cells," 12th International Workshop on Computational Electronics: Oct. 8-10, 2007.
  • T. D. Drysdale, A. R. Brown, S. Roy, G. Roy and A. Asenov, "Capacitance variability of short range interconnects," Journal of Computational Electronics, Dec. 2007.
  • S. Markov, A. R. Brown, B. Cheng, G. Roy, S. Roy and A. Asenov, "Three-dimensional statistical simulation of gate leakage fluctuations due to combined interface roughness and random dopants," Japanese Journal of Applied Physics Part 1-Regular Papers Brief Communications & Review Papers, Vol. 46, No. 4B, pp. 2112–2116, 2007.
  • C. Millar, S. Roy, A. R. Brown and A. Asenov, "Simulating the bio-nanoelectronic interface," Journal of Physics-Condensed Matter, Vol. 19, No. 21, 2007.
  • C. Riddet, A. R. Brown, C. L. Alexander, J. R. Watling, S. Roy and A. Asenov, "3-D Monte Carlo simulation of the impact of quantum confinement scattering on the magnitude of current fluctuations in double gate MOSFETs," IEEE Transactions on Nanotechnology, Vol. 6, No. 1, pp. 48–55, 2007.
  • C. Riddet, A. R. Brown, S. Roy and A. Asenov, "Boundary conditions for density gradient corrections in 3D Monte Carlo simulations," 12th International Workshop on Computational Electronics: Oct. 8-10, 2007.
  • K. Samsudin, F. Adamu-Lema, A. R. Brown, S. Roy and A. Asenov, "Combined sources of intrinsic parameter fluctuations in sub-25 nm generation UTB-SOI MOSFETs: A statistical simulation study," Solid-State Electronics, Vol. 51, No. 4, pp. 611–616, 2007.
  • R. O. Sinnott, A. Asenov, A. R. Brown, C. Millar, S. Roy, G. Roy and G. Stewart, "Grid Infrastructures for the Electronics Domain: Requirements and Early Prototypes from an EPSRC Pilot Project," in Proc. UK e-Science All Hands Meeting, Nottingham, UK, 2007, pp. 509–516.

2006

  • A. Asenov, A. R. Brown, G. Roy, C. L. Alexander and A. Martinez, "Simulation of Atomic Scale Effects and Fluctuations in nano-scale CMOS," in Proc. Solid-State Devices and Materials (SSDM), Yokohama, Japan, Sept. 12-15, 2006, pp. 358–359.
  • A. Asenov, A. R. Brown, B. Cheng, J. R. Watling, G. Roy and C. L. Alexander, "Simulation of nano-CMOS devices: from atoms to architecture," in Nanotechnology for Electronic Materials and Devices, A. Korkin, J. Labanowski, E. Gusev and S. Luryi, Eds. New York: Springer, 2006, pp. 257–303.
  • A. R. Brown, J. R. Watling and A. Asenov, "Intrinsic Parameter Fluctuations due to Random Grain Orientations in High-k Gate Stacks," J. Computational Electronics, Vol. 5, pp. 333–336, 2006.
  • A. R. Brown, J. R. Watling and A. Asenov, "Intrinsic Parameter Fluctuations due to Random Grain Orientations in High-k Gate Stacks," in Proc. Book of Abstracts of the 11th International Workshop on Computational Electronics (IWCE), Vienna, Austria, May 25-27, 2006, pp. 49–50.
  • A. R. Brown, G. Roy and A. Asenov, "Impact of Fermi level pinning at polysilicon gate grain boundaries on nano-MOSFET variability: A 3-D simulation study," in Proc. 36th European Solid-State Device Research Conference (ESSDERC), Montreux, Switzerland, Sept. 19-21, 2006, pp. 451–454.
  • B. Cheng, S. Roy, G. Roy, A. R. Brown and A. Asenov, "Design Consideration of 6-T SRAM towards the End of Bulk CMOS Technology Scaling Subjected to Random Dopant Fluctuation," in Proc. Proc 36th European Solid-State Device Research Conference (ESSDERC),
  • S. Markov, A. R. Brown, B. Cheng, G. Roy, S. Roy and A. Asenov, "3D statistical simulation of gate leakage fluctutations due to combined interface roughness and random dopants," in Proc. Solid-State Devices and Materials (SSDM), Yokohama, Japan, Sept. 12-15, 2006, pp. 362–363.
  • A. Martinez, J. R. Barker, A. Svizhenko, M. P. Anantram, A. R. Brown, B. Biegel and A. Asenov, "The unintentional discrete charges in a nominally undoped channel of a thin body double gate MOSFET: Classical to Full Quantum Simulation," Journal of Physics Conferences Series, Vol. 38, pp. 192–195, 2006.
  • C. Riddet, A. R. Brown, C. L. Alexander, S. Roy and A. Asenov, "Efficient density gradient quantum corrections for 3D Monte Carlo simulations," ser. International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2006, California,USA,
  • G. Roy, A. R. Brown, F. Adamu-Lema, S. Roy and A. Asenov, "Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs," IEEE Transactions on Electron Devices, Vol. 53, No. 12, pp. 3063–3070, 2006.
  • G. Roy, A. R. Brown, F. Adamu-Lema, S. Roy and A. Asenov, "Intrinsic Parameter Fluctuations in Conventional MOSFETs until end of the ITRS," Journal of Physics Conferences Series, Vol. 38, pp. 188–191, 2006.
  • K. Samsudin, F. Adamu-Lema, A. R. Brown, S. Roy and A. Asenov, "Intrinsic parameter fluctuations in sub-10nm generation UTB SOI MOSFETs," ser. 7 th European Workshop on ULtimate Integration of Silicon , ULIS 2006, pp. 93–96.
  • K. Samsudin, B. Cheng, A. R. Brown, S. Roy and A. Asenov, "Sub-25 nm UTB SOISRAM cell under the influence of discrete random dopants," Solid-State Electronics, Vol. 50, No. 4, pp. 660–667, 2006.
  • K. Samsudin, B. Cheng, A. R. Brown, S. Roy and A. Asenov, "Integrating intrinsic parameter fluctuation description into BSIMSOI to forecast sub-15 nm UTB SOI based 6T SRAM operation," Solid-State Electronics, Vol. 50, No. 1, pp. 86–93, 2006.

2005

  • C. L. Alexander, A. R. Brown, J. R. Watling and A. Asenov, "Impact of single charge trapping in nano-MOSFETs - Electrostatics versus transport effects," IEEE Transactions on Nanotechnology, Vol. 4, No. 3, pp. 339–344, 2005.
  • C. L. Alexander, A. R. Brown, J. R. Watling and A. Asenov, "Impact of scattering in 'atomistic' device simulations," Solid-State Electronics, Vol. 49, No. 5, pp. 733–739, 2005.
  • J. R. Barker, J. R. Watling, A. R. Brown, S. Roy, P. Zeitzoff, G. Bersuker and A. Asenov, "Monte Carlo study of couples SO phonon-plasmon scattering in Si MOSFETs with high-k dielectric gate stacks: hot electron and disorder effects," in Proc. 14th International Conference on Hot Carriers in Semiconductors (HCIS14), July p. TU 4–2.
  • A. R. Brown, A. Asenov, S. Roy and J. R. Barker, "Parallel 3D finite element power semiconductor device simulator based on topologically rectangular grid," in Proc. Simulation of Semiconductor Devices and Processes, 2005, pp. 336–339.
  • A. R. Brown, J. R. Watling, A. Asenov, G. Bersuker and P. Zeitzoff, "Intrinsic parameter fluctuations in MOSFETs due to structural non-uniformity of high-k gate stack materials," in Proc. 2005 International Conference on Simulation of Semiconductor Processes and Devices, Tokyo, Japan, Sept. 1-3, 2005, pp. 27–30.
  • A. Martinez, J. R. Barker, A. Svizhenko, M. P. Anantram, A. R. Brown, B. Biegel and A. Asenov, "The impact of unintentional discrete charges in a nominally undoped channel of a thin body double gate MOSFETS: Classical to full quantum simulation," ser. New Phenomena in Mesoscopic Structures - 7 (NPMS) and the fifth in the series of Surfaces and Interfaces of Mesoscopic Devices (SIMD), NPMS-7/ SIMD-5,
  • A. Martinez, A. Svizhenko, M. P. Anantram, J. R. Barker, A. R. Brown, B. Biegel and A. Asenov, "Impact of stray charges on the characteristics of nano-DGMOSFETs in the ballistic regime: A NEGF simulation study," ser. Silicon Nanoelectronics Workshop 2005, pp. 76–77.
  • A. Martinez, A. Svizhenko, M. P. Anantram, J. R. Barker, A. R. Brown and A. Asenov, "A study of the effect of interface roughness on a DG-MOSFET using full 2D NEGF technique," in Proc. IEDM 2005 Tech. Dig. pp. 627-630,
  • C. Millar, A. Asenov, S. Roy and A. R. Brown, "Simulating the bio-nano-CMOS interface," ser. 5th IEEE conference on Nanotechnology, Nagoya, Japan,
  • C. Millar, A. Asenov, A. R. Brown and S. Roy, "Tracking the propagation of individual ions through nano-MOSFETs," J. Computational Electronics, Vol. 4, No. 1-2, pp. 185–188, Apr. 2005.
  • C. Riddet, A. R. Brown, C. L. Alexander, J. R. Watling, S. Roy and A. Asenov, "Impact of quantum confinement scattering on the magnitude of current fluctuations in double gate MOSFETs," ser. Silicon Nanoelectronics Workshop 2005,
  • G. Roy, F. Adamu-Lema, A. R. Brown, S. Roy and A. Asenov, "Simulation of combined sources of intrinsic parameter fluctuations in 'real' 35nm MOSFET," ser. European Solid-State Device Research Conference 2005 - ESSDERC2005, Grenoble, France,
  • G. Roy, F. Adamu-Lema, A. R. Brown, S. Roy and A. Asenov, "Intrinsic parameter fluctuations in conventional MOSFETs until the end of the ITRS," ser. New Phenomena in Mesoscopic Structures - 7 (NPMS) and the fifth in the series of Surfaces and Interfaces of Mesoscopic Devices (SIMD), NPMS-7/ SIMD-5,
  • K. Samsudin, B. Cheng, A. R. Brown, S. Roy and A. Asenov, "Impact of random dopant induced fluctuations on sub-15nm UTB SOI 6T SRAM cells," 2005 IEEE International SOI Conference, Proceedings, pp. 61–62, 2005.
  • K. Samsudin, B. Cheng, A. R. Brown, S. Roy and A. Asenov, "UTB SOI SRAM cell stability under the influence of intrinsic parameter fluctuation," ser. European Solid-State Device Research Conference 2005 - ESSDERC2005, Grenoble, France, pp. 553–556.
  • K. Samsudin, B. Cheng, A. R. Brown, S. Roy and A. Asenov, "Impact of body thickness fluctuation in nanometre scale UTB SOI MOSFETs on SRAM cell functionality," in Proc. 6th European Conference on Ultimate Integration of Silicon (ULIS05), Apr.
  • J. R. Watling, A. R. Brown, C. L. Alexander, G. Ferrari, J. R. Barker, G. Bersuker, P. Zeitzoff and A. Asenov, "Electrostatic and transport variations in nano CMOS devices due to variations in high-k oxides," ser. 2nd International Workshop on Advanced Gate Stack Technology, Texas, USA,

2004

  • F. Adamu-Lema, S. Roy, A. R. Brown, A. Asenov and G. Roy, "Intrinsic parameter fluctuations in conventional MOSFETs at the scaling limit: a statistical study," in Proc. 10th International Workshop on Computational Electronics (IWCE), West Lafayette, IN, USA, Oct. 24-27, 2004, pp. 44–45.
  • F. Adamu-Lema, G. Roy, A. R. Brown, A. Asenov and S. Roy, "Intrinsic parameter fluctuations in conventional MOSFETs at the scaling limit:a statistical study," J. Computational Electronics, Vol. 3, pp. 203–206, 2004.
  • C. L. Alexander, A. R. Brown, J. R. Watling and A. Asenov, "Impact of scattering on random dopant induced current fluctuations in decanano MOSFETs," in Proc. SISPAD, ser. Simulation of Semiconductor Processes and Devices, pp. 223–226.
  • C. L. Alexander, A. R. Brown, J. R. Watling and A. Asenov, "Impact scattering in 'atomistic' device simulation," in Proc. Ultimate Intigration of Silicon, ser. 5th European Workshop on Ultimate Integration of Silicon - ULIS04,
  • C. L. Alexander, A. R. Brown, J. R. Watling and A. Asenov, "Impact of single charge trapping in nano-MOSFETs," in Proc. Silicon Nanoelectronics Workshop, ser. IEEE 2004 Silicon Nanoelectronics Workshop, Honolulu,
  • C. L. Alexander, A. R. Brown, J. R. Watling and A. Asenov, "Impact of scattering in 'atomistic' device simulation," in Proc. Proc. ULIS 2004, Leuven Belgium, pp. 89–92.
  • A. Asenov, G. Roy, C. L. Alexander, A. R. Brown, J. R. Watling and S. Roy, "Quantum mechanical and transport aspects of resolving discrete charges in nano-CMOS device simulation," in Proc. 4th IEEE Conference on Nanotechnology (IEEE Nano), Munich, Germany, Aug. 17-19, 2004, pp. 334–336.
  • A. Asenov, A. R. Brown and S. Kaya, "Atomistic Simulation of Decanano MOSFETs," in Predictive Simulation of Semiconductor Processing: Status and Challenges, J. Dabrowski and E. R. Weber, Eds. Berlin: Springer, 2004, pp. 111–156.
  • A. Lee, A. R. Brown, A. Asenov and S. Roy, "RTS amplitudes in decanano n-MOSFETs with conventional and high- k gate stacks," ser. Conference on Solid State Devices and Materials - SSDM 2004,
  • A. Lee, A. R. Brown, A. Asenov and S. Roy, "RTS amplitudes in decanano n-MOSFETs with conventional and high-k gate stacks," J. Computational Electronics, Vol. 3, pp. 247–250, 2004.
  • A. Lee, A. R. Brown, A. Asenov and S. Roy, "RTS amplitudes in decanano n-MOSFETs with conventional and high-k gate stacks," in Proc. International Workshop on Computational Electronics (IWCE 10), Oct. pp. 159–160.
  • C. Millar, A. Asenov, A. R. Brown and S. Roy, "Tracking the propagation of individual ions through ion channels with nano-MOSFETs," in Proc. 10th International Workshop on Computational Electronics (IWCE), ser. International workshop on Computational Electronics, IWCE-10, West Lafayette, IN, USA, Oct. 24-27, 2004, pp. 205–206.
  • C. Riddet, A. R. Brown, C. L. Alexander, J. R. Watling, S. Roy and A. Asenov, "Scattering from body thickness fluctuations in double gate MOSFETs. An ab initio Monte Carlo simulation study," ser. International workshop on Computational Electronics, IWCE-10, West Lafayette, USA, pp. 194–195.
  • C. Riddet, A. R. Brown, C. L. Alexander, J. R. Watling, S. Roy and A. Asenov, "Scattering From Body Thickness Fluctuations in Double Gate MOSFETs. An ab initio Monte Carlo Study." J. Comp. Elec, Vol. 3, pp. 341–345, 2004.

2003

  • C. L. Alexander, A. R. Brown, J. R. Watling and A. Asenov, "Artificial carrier heating due to the introduction of ab-initio Coulomb scattering in Monte Carlo simulations." Superlattices and Microstructures, Vol. 34, No. 3-6, pp. 319–326, 2003.
  • A. Asenov, A. R. Brown, J. H. Davies, S. Kaya and G. M. Slavcheva, "Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs," IEEE Transactions on Electron Devices, Vol. 50, No. 9, pp. 1837–1852, 2003.
  • A. Asenov, S. Kaya and A. R. Brown, "Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness," IEEE Transactions on Electron Devices, Vol. 50, No. 5, pp. 1254–1260, 2003.
  • A. Asenov, R. Balasubramaniam, A. R. Brown and J. H. Davies, "RTS amplitudes in decananometer MOSFETs: 3-D Simulation Study," IEEE Transactions on Electron Devices, Vol. 50, No. 3, pp. 839–845, 2003.
  • A. Asenov, A. R. Brown and J. R. Watling, "Quantum corrections in the simulation of decanano MOSFETs," Solid-State Electronics, Vol. 47, No. 7, pp. 1141–1145, 2003.
  • A. Asenov, A. R. Brown, J. H. Davies, S. Kaya and G. M. Slavcheva, "Simulation of Intrinsic Parameter Fluctuations in Decananometre and Nanometre scale MOSFET's." IEEE Trans. Electron Dev. Vol. 50, pp. 1837–1852, 2003.
  • A. Asenov, J. R. Watling, A. R. Brown and D. K. Ferry, "The Use of Quantum Potentials for Confinement and Tunnelling in Semiconductor Devices," J. Computational Electronics, Vol. 1, pp. 503–513, 2003.
  • A. R. Brown, F. Adamu-Lema and A. Asenov, "Intrinsic parameter fluctuations in nanometer scale thin body SOI devices introduced by interface roughness," in Proc. Sixth International Conference on New Phenomena in Mesoscopic Systems, and Fourth International Conference on Surfaces and Interfaces of Mesoscopic Devices (NPMS-6/SIMD-4), Maui, HI, USA, Nov. 30-Dec. 5, 2003, pp. 32–33.
  • A. R. Brown, F. Adamu-Lema and A. Asenov, "Intrinsic parameter fluctuations in UTB MOSFETs induced by body thickness variations," in Proc. Silicon Nanoelectronics Workshop, Kyoto, Japan, June 8-9, 2003,
  • A. R. Brown, F. Adamu-Lema and A. Asenov, "Intrinsic Parameter Fluctuations in Nanometre Scale Thin-body SOI Devices Introduced by Interface Roughness," Superlattices and Microstructures, Vol. 34, No. 3-6, pp. 283–291, 2003.
  • A. Lee, A. R. Brown, A. Asenov and S. Roy, "RTS noise simulations of decanano MOSFETs subject to atomic scale structure variations," ser. NPMS-6/SIMD-4 Sixth International Conference on New Phenomena in Mesoscopic Systems, and Fourth International Conference on Surfaces and Interfaces of Mesoscopic Devices, Maui, Hawaii,
  • A. Lee, A. R. Brown, A. Asenov and S. Roy, "RTS noise simulations of decanano MOSFET's subject to atomic scale structure variations." Superlattices and Microstructures, Vol. 34, No. 3-6, 2003.
  • G. Roy, A. R. Brown, A. Asenov and S. Roy, "Bipolar quantum corrections in resolving individual dopants in atomistic, intrinsic parameter fluctuations into compact model circuit analysis," ser. NPMS-6/SIMD-4 Sixth International Conference on New Phenomena in Mesoscopic Systems, and Fourth International Conference on Surfaces and Interfaces of Mesoscopic Devices, Maui, Hawaii, pp. 34–35.
  • G. Roy, A. R. Brown, A. Asenov and S. Roy, "Quantum aspects of resolving discrete charges in atomistic device simulation," Journal of Computational Electronics, Vol. 2, pp. 323–327, 2003.
  • G. Roy, A. R. Brown, A. Asenov and S. Roy, "Bipolar quantum corrections in resolving individual dopants in 'atomistic' device simulations," Superlattices and Microstructures, Vol. 34, No. 3-6, pp. 327–334, 2003.
  • G. Roy, A. R. Brown, A. Asenov and S. Roy, "Quantum aspects of resolving discrete charges in “atomistic” device simulation," in Proc. Extended abstracts of the International Workshop on Computational Electronics IWCE-9,
  • S. Roy, A. Lee, A. R. Brown and A. Asenov, "Application of quasi-3D and 3D MOSFET simulations in the atomistic regime," ser. International Workshop on Computational Electronics - IWCE 9,
  • S. Roy, A. Lee, A. R. Brown and A. Asenov, "Application of quasi-3D and 3D MOSFET simulations in the atomistic regime," Journal of Computational Electronics, Vol. 2, pp. 423–426, 2003.
  • J. R. Watling, A. Asenov, A. R. Brown, A. Svizhenko and M. P. Anantram, "Direct Source-to-Drain Tunnelling and its Impact on the Intrinsic Parameter Fluctuations in nanometre scale Double Gate MOSFETs," in Proc. Proc. Modeling and Simulation of Microsystems (MSM03), p. 202.

2002

  • A. Asenov, S. Kaya and A. R. Brown, "Implications of Imperfect Interfaces and edges in Ultra-small MOSFET characteristics," Physica Status Solidi B, Vol. 233, No. 1, pp. 101–112, 2002.
  • A. Asenov, M. Jaraiz, S. Roy, G. Roy, F. Adamu-Lema, A. R. Brown, V. Moroz and R. Gafiteanu, "Integrated atomistic process and device simulation of decananometre MOSFETs," in Proc. Simulation of Semiconductor Processes and Devices, Kobe, Japan, Sept. 4-6, 2002, pp. 87–90.
  • A. Asenov, A. R. Brown and J. R. Watling, "Quantum corrections in the simulation of decanano MOSFETs," in Proc. 3rd European Workshop on Ultimate Integration of Silicon (ULIS), Munich, Germany, 2002,
  • A. Asenov, A. R. Brown and J. R. Watling, "The Use of Quantum Potentials for Confinement in Semiconductor Devices," in Proc. 5th International Conference on Modeling and Simulation of Microsystems (MSM), Puerto Rico, Apr. 20-25, 2002,
  • A. R. Brown, J. R. Watling and A. Asenov, "A 3-D atomistic study of archetypal double gate MOSFET structures," Journal of Computational Electronics, Vol. 1, pp. 165–169, 2002.
  • A. R. Brown, A. Asenov and J. R. Watling, "Intrinsic Fluctuations in Sub 10 nm Double-Gate MOSFETs Introduced by Discreteness of Charge and Matter," IEEE Trans. Nanotechnology, Vol. 1, pp. 195–200, 2002.
  • A. R. Brown, A. Asenov and J. R. Watling, "Intrinsic Fluctuations in Sub 10 nm Double-Gate MOSFETs Introduced by Discreteness of Charge and Matter," in Proc. Silicon Nanoelectronics Workshop, Honolulu, HI, USA, June 9-10, 2002,
  • G. M. Slavcheva, J. H. Davies, A. R. Brown and A. Asenov, "Potential fluctuations in metal-oxide-semiconductor field-effect transistors generated by random impurities in the depletion layer," Journal of Applied Physics, Vol. 91, pp. 4326–4334, 2002.
  • G. M. Slavcheva, J. H. Davies, A. R. Brown and A. Asenov, "Statistics of the random potential fluctuations in the MOSFET channel," in Proc. 26th International Conference on Physics of Semiconductors, ser. 26th International Conference on Physics of Semiconductors, Edinburgh, UK, June 29-Aug. 3, 2002,
  • G. M. Slavcheva, J. H. Davies, A. R. Brown and A. Asenov, "Potential fluctuations in MOSFET's generated by randomly distributed impurities in the depletion layer." Journal of Applied Physics, Vol. 91, pp. 4326–4334, 2002.
  • J. R. Watling, A. R. Brown and A. Asenov, "Can the density gradient approach describe the source-drain tunnelling in decanano double-gate MOSFETs?" J. Computational Electronics, Vol. 1, pp. 289–293, 2002.
  • J. R. Watling, A. R. Brown, A. Asenov, A. Svizhenko and M. P. Anantram, "Simulation of Direct Source-to-Drain Tunnelling Using the Density Gradient Formalism: Non-equilibrium Green's Function Calibration," in Proc. Proc. SISPAD 2002, IEEE Cat. no. 02TH8621, pp. 267–270.

2001

  • A. Asenov, G. M. Slavcheva, A. R. Brown, J. H. Davies and S. Saini, "Quantum enhancement of the random dopant induced threshold voltage fluctuations in sub 100nm MOSFETs: A 3-D density-gradient simulation study," IEEE Transactions on Electron Devices, Vol. 48, No. 4, pp. 722–729, 2001.
  • A. R. Brown, J. R. Watling and A. Asenov, "A 3-D atomistic study of archetypal double gate MOSFET structures," in Proc. 8th International Workshop on Computational Electronics (IWCE), Urbana-Champaign, IL, USA, Oct. 15-17, 2001,
  • A. R. Brown, S. Kaya, A. Asenov, J. H. Davies and T. Linton, "Statistical Simulation of Line Edge Roughness in Decanano MOSFETs," in Proc. Silicon Nanoelectronics Workshop, Kyoto, Japan, June 10-11, 2001,
  • S. Kaya, A. R. Brown, A. Asenov, D. Magot and T. Linton, "Analysis of Statistical Fluctuations Due to Line Edge Roughness in Sub-0.1μm MOSFETs," in Proc. Simulation of Semiconductor Processes and Devices (SISPAD 2001), pp. 78–81.
  • J. R. Watling, A. R. Brown, A. Asenov and D. K. Ferry, "Quantum corrections in 3-D drift diffusion simulation of decanano MOSFETs using an effective potential," ser. Simulation of semiconductor processes and devices, Vienna, pp. 81–85.

2000

  • A. Asenov, R. Balasubramaniam, A. R. Brown and J. H. Davies, "Effect of Single electron trapping in decanano MOSFETs: A 3D “atomistic” simulation study," Superlattices and Microstructures, Vol. 27, No. 5/6, pp. 411–416, 2000.
  • A. Asenov, G. M. Slavcheva, A. R. Brown, R. Balasubramaniam and J. H. Davies, "Statistical, 3D “atomistic” simulation of decanano MOSFETs," Superlattices and Microstructures, Vol. 27, No. 2/3, pp. 215–227, 2000.
  • A. Asenov, R. Balasubramaniam, A. R. Brown, J. H. Davies and S. Saini, "Random Telegraph Signal Amplitudes in Sub 100nm (Decanano) MOSFETs: a 3D Atomistic Simulation Study," in Proc. IEDM Tech. Digest, 2000, pp. 279–282.

1999

  • A. Asenov, A. R. Brown, J. H. Davies and S. Saini, "Hierarchical approach to “atomistic” 3D MOSFET simulation," IEEE Trans. Computer-Aided Design of Intergrated Circuits and Systems, Vol. 18, pp. 1558–1565, 1999.
  • A. Asenov, G. M. Slavcheva, A. R. Brown and J. H. Davies, "Quantum Mechanical Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations and Lowering in Sub 0.1 micron MOSFETs," in Proc. IEDM Tech. Digest, 1999, pp. 535–538.

1998

  • A. Asenov, A. R. Brown and S. Roy, "Parallel semiconductor device simulation: from power to atomistic devices," in Proc. 6th International Workshop on Computational Electronics (IWCE), Osaka, Japan, Oct. 19-21, 1998, pp. 58–61.
  • A. Asenov, A. R. Brown, S. Roy and J. R. Barker, "Topologically rectangular grids in the parallel simulation of semiconductor devices," VLSI Design, Vol. 6, No. 1-4, pp. 91–95, 1998.
  • A. R. Brown, A. Asenov and J. R. Barker, "3D parallel finite element simulation of in-cell breakdown in lateral-channel IGBTs," VLSI Design, Vol. 8, No. 1-4, pp. 99–103, 1998.

1997

  • A. Asenov, A. R. Brown, S. Roy, C. R. Arokianathan, J. H. Davies and J. R. Barker, "Parallel 3D Simulation of Semiconductor Devices," in Proc. 2nd NASA Device Modeling Workshop, Ames Research Center, Moffet Field, CA, USA, 1997, pp. 85–99.

1996

  • A. Asenov, J. R. Barker, A. R. Brown and G. L. Lee, "Scalable parallel 3D finite element nonlinear Poisson solver," Journal of Simulation Practice and Theory, Vol. 45, pp. 155–168, 1996.
  • A. Asenov, A. R. Brown, S. Roy and J. R. Barker, "Topically Rectangular Finite Element Grids in the Parallel Simulation of Semiconductor Devices," in Proc. Computational Mechanics in UK, 4th ACME Annual Conference, Jan. 4-5, 1996, pp. 49–52.
  • S. Roy, A. Asenov, A. R. Brown and J. R. Barker, "Partitioning of Topologically Rectangular Finite Element Grids," in Proc. Proc. Computational Mechanics in UK, 4th ACME Annual Conference, pp. 41–44.

1995

  • A. R. Brown, A. Asenov, S. Roy and J. R. Barker, "Development of a parallel 3D finite element power semiconductor device simulator," in Proc. IEE Colloquium on Physical Modeling of Semiconductor Devices, Digest No. 1995/064, 1995, p. 2/1–2/6.
  • A. R. Brown, A. Asenov, S. Roy and J. R. Barker, "Parallel 3D finite element power semiconductor device simulator based on topologically rectangular grid," in Proc. Simulation of Semiconductor Devices and Processes, 2005, pp. 336–339.

1994

  • A. Asenov, J. R. Barker, A. R. Brown and G. L. Lee, "Scalable parallel 3D finite element nonlinear Poisson solver," in Proc. Massively Parallel Processing, Applications and Development, pp. 665–672.
  • A. Asenov, J. R. Barker and A. R. Brown, "Parallel 3D finite element simulation of nano-structured devices," in Proc. NASECODE X, pp. 52–53.
  • J. R. Barker, A. Asenov, A. R. Brown, J. Cluckie, S. Babiker and C. R. Arokianathan, "Parallel simulation of semiconductor devices," in Proc. Massively Parallel Processing, Applications and Development, pp. 683–690.
  • A. R. Brown, A. Asenov, J. R. Barker, P. Waind and D. E. Crees, "Calibration of the numerical simulations in the design of high temperature IGBTs," in Proc. 2nd International Seminar on Power Semiconductors (ISPS), Prague, Czech Republic, Aug. 31-Sept. 2, 1994, pp. 151–157.

1993

  • A. R. Brown, A. Asenov, J. R. Barker, S. Jones and P. Waind, "Numerical simulation of IGBTs at elevated temperatures," in Proc. 2nd International Workshop on Computational Electronics (IWCE), Leeds, UK, Aug. 11-13, 1993, pp. 50–55.
  • A. R. Brown, D. Reid, A. Asenov and J. R. Barker, "The implementation and speed-up of coloured SOR methods for solving 3D Poisson equation on an array of transputers," in Proc. 2nd International Workshop on Computational Electronics (IWCE), Aug. 11-13, 1993, pp. 173–176.