September 2021

Congratulations to Christian and Rakshita

Christian and Rakshita have oral presentation and comferance paper accepted to :

Both papers are linked to two ouf our EU projects: DESIGN-EID and ELECTROMED

June 2021

Congratulations to Enrico

Enrico gave an exellent talk and presentation at at Swiss NanoConvention 2021 conference wich show the work in our EU project: DESIGN-EID

The talk can be found here


June 2021

Congratulations to Paul, Rakshita and Christian 

Well done to Paul, Rakshita and Christian for having their conference abstracts accepted for oral presentations at EuroSOI-ULIS 2021 conference. Let's hope that we will be able to go to France to present.

April 2021

Seminar to Glasgow University Engineering Society

Vihar will give a seminar on 8th April 2021 to everyone in the School about the work in the group

Here is the link to recording 


March 2021

Welcome to Naveen Kumar- our new PDRA

We would like to welcome Naveen who is joining us from Dr B R Ambedkar National Institute of Technology Jalandhar, India.

February 2021

New Video from DESIGN-EID ITN EUH2020 project 

Christian made a very nice video which explains his work in our DESIGN-EID project 

February 2021

Congratulations to Paul 

He published his first paper as a first author. Well done to everyone!

September 2020

Welcome to Cristina Martínez Oliver, Christian Dam Vedel and Enrico Brugnolotto - our new PhD students and Early Stage Researchers (ESR)

They will work on MSCA EU project - DESIGN-EID

August 2020

Welcome to Ali Rezaei- our new PDRA

We would like to welcome Ali who is joining us from Universität Konstanz, Germany.

July 2020

Congratulations to Asen & Vihar

Asen & Vihar won another EPSRC grant which is in collaboration with our friends from Liverpool John Moores University. The title of the grant is "Realistic fault modelling to enable optimization of low power IoT and Cognitive fault-tolerant computing systems". 

April 2020

Welcome to Daniel Nagy- our new PDRA

We would like to welcome Daniel who is joining us from Universidade de Santiago de Compostela, Spain.

June 2019

Congratulations to everyone

Congratulations to everyone in Device Modelling Group. We have 6 oral and 1 poster presentations accepted for SISPAD conference in Udine. Well done to everyone and keep working very hard!

May 2018

Congratulations to Vihar

Vihar won highly competitive UKRI Innovation Fellowship which is targeted at early career researchers across the UK, providing funds (~£780k FEC) for three years to nurture future leaders in both industry and academia.

May 2018

Congratulations to everyone

Ten papers from our group are accepted for SISPAD 2018. 

April  2018

Welcome to Oves - our new PDRA

We would like to welcome Oves who is joining us from University of Udine, Italy.

September  2017

Welcome to Tapas - our new PDRA

We would like to welcome Tapas who is joining us from Indian Institute of Technology, Kanpur, India.

July 2017

Welcome to Cristina - our new PDRA

We would like to welcome Cristina who is joining us from University of Granada, Spain. 

June   2017

Welcome to Hamiton - our new PDRA

We would like to welcome Hamiton who is joining us from EHT Zurich, Switzerland

June   2017

Congratulations to everyone

Five papers from our group are accepted in SISPAD 2017. 

February   2017

Congratulations to Talib

He won a gold medal from Iraqi regional cultural attaché.

The Iraqi regional cultural attaché in London had a meeting and celebration with students studying in the United Kingdom and Ireland on 24-01-17. The meeting was with the Minister of Higher Education and Scientific Research (Iraq), accompanied by Minister of Oil and the Ambassador of the Republic of Iraq, and the Counsellor Attaché. During the ceremony, some postgraduate students who have at least eight publications during the period of their studies were recognised and received an award. Iraqi student societies who had various achievements were also honoured. The total number of Iraqi student in the UK and Ireland is 2495. About 30 of them study at the University of Glasgow. The number of students who attended that meeting was about 70, and 12 of them received an award. Three of them are studying at the University of Glasgow, School of Engineering. 


(from left)  Dr. Hassan Al Alak (Counsellor Cultural Attache of Iraq), Talib Al-Ameri (Device modelling group), Mr. Jabbar Luaibi (Minister of Oil ), Prof. Abdul Razak Abdul Jalil Al-Issa (Minister of Higher Education and Scientific Research of Iraq), Dr Salih Husain Ali Al-Tamimi ( Ambassador of Iraq in the UK).

November 2016

Congratulations to Vihar

He won EPSRC Fisrt Grant Scheme

September 2016

Welcome Jaehyun, Meng and Salim to the group

Our new Post Doctoral Research Associate (PDRA)

June 2016

Congratulations and welcome Alex to the group

A winner of EPSRC Summer Vacation Scholarship 2016! 

January 2016

New Openings

  We are currentlly looking for PhD & Post-Doc colleagues interested in the area of device modelling.

  Avaiable PhD projects:

Device Modelling Group starts work on three EC HORIZON 2020 projects:

  • CONNECT    (CarbON Nanotube compositE InterconneCTs)
  • REMINDER  (Revolutionary embedded memory for internet of things devices and energy reduction)
  • SUPERAID7 (Stability Under Process Variability for Advanced Interconnects and Devices Beyond 7 nm node)


June 2015

Cover story in a special issue on "Variation aware technology and circuit co-design" of IEEE T-ED


Our pictures are highlighted in the front cover of Special Issue on "Variation Aware Technology and Circuit Co-Design" in IEEE Transactions on Electron Devices, Vol. 62 No. 6. in June 2015 [1]. The pictures highlight the interplay between global long-range process-induced variability and local short-range statistical variability in 14 nm FinFET technology and it leads to the deviation of Pelgrom's area dependence of mismatch reported in [2]. The complicated variability issue requires design-technology co-optimisation (DTCO). The novel DTCO practices are carried out and reported in [1].

[1] A. Asenov, B. Cheng, X. Wang, A.R. Brown, C. Millar, C. Alexander, S. M. Amoroso, J.B. Kuang, and S. Nassif, “Variability aware simulation based design-technology co-optimisation (DTCO) flow in 14 nm FinFET/SRAM co-optimisation,” IEEE Transactions on Electron Devices. Vol. 62 No. 6, pp.1682-1690, June 2015. (Invited Paper)

[2] X. Wang, B. Cheng, A. R. Brown, C. Millar, J. B. Kuang, S. Nassif, and A. Asenov, “Interplay Between Process-Induced and Statistical Variability in 14-nm CMOS technology Double-Gate SOI FinFETs,” IEEE Transactions on Electron Devices, Vol.60 No.8, pp.2485-2492, August 2013.

The link to the front cover.


11th Sep 2012

Two Day Course on Device Variability at the University of Glasgow, 19-20th November 2012


Device Variability And Its Impact on Circuits and Electronic Systems.

Timetable, location and registration now available.

20th Aug 2012

Two Day Course on Device Variability at the University of Glasgow, 19-20th November 2012


Device Variability And Its Impact on Circuits and Electronic Systems.

The course is organized by StatDes (Statistical Design and Verification of Analogue Systems) knowledge transfer project in collaboration with IBM, Wolfson Micro Electronics, Gold Standard Simulations, the University of Edinburgh and the University of Glasgow. It will cover the fundamental physics of variability in modern day transistors of different architectures and their impact on digital and analogue systems. Moreover, the adverse effects of such fluctuations in SRAM circuits will also be covered in the course. Detail will be announced shortly.

7th Jun 2012

Device Modelling at VARI 2012


LogoVari.pngThe 3rd European Workshop on CMOS Variability, VARI 2012, is taking place in Nice from the 11-12 June 2012, and the Device Modelling Group is contributing 4th papers.

Professor Asen Asenov opens the conference with a keynote presentation entitled "Device-Circuit Interplay in the Simulation of Statistical CMOS Variability". This is followed on the first day by papers from Yunxiang Yang (a collaboration between Peking University, Device Modelling and Gold Standard Simulations) on 22nm UTBB SOI variablity and Jie Ding's paper "Statistical Compact Model Extraction in the Presence of BTI Degradation". On the second day of the conference Plamen Asenov will present a further paper on statistical compact model extraction.

6th Dec 2011

SOI FinFets posied to meet variability requirements of 11nm CMOS

  A joint paper between the Device Modelling Group and Gold Standard Simulations, Ltd (GSS) presented at the International Electron Devices Meeting (IEDM) held this week reveals that SOI FinFETs are poised to meet the low statistical variability requirements of 11nm CMOS technology.

Electronics Weekly: SOI finfet will scale to 11nm, says Asenov.
Compute Scotland: SOI FinFETs for 11nm CMOS.