Greg Taylor (Intel Labs) SISPAD'13

"Analog Design in Deeply Scaled CMOS"      

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StatDesLogo.png Statistical Design and Verification of Analogue Systems


STATDES_all.pngWith decades of research, manufacturing efforts and successes of transistor miniaturization by the leading Semiconductor Industries and research groups comes the “cramming” of large-scale transistors into a single chip, which results in more and more powerful chips. However, smaller transistors are far more variable and less reliable. This is one of the major challenges to the design, development and manufacturing of such advanced chips, to which there is no easy solution. This problem is exacerbated by a strong demand for smaller devices with more functionality from consumer electronics companies, which is reflected by the surge of great popularity of, for example, iPhones, iPods, iPads and other digital media products.


The overarching vision of StatDes as knowledge transfer project is to deliver competitive advantage, innovation and growth to the Scottish electronic design industry by translating leading edge EPSRC-funded transformative research in statistical CMOS “variability aware design” into advanced analogue, mixed signal and low power design capabilities.

Aim and Objectives

StatDes will draw on several years of pioneering academic work by Universities of Glasgow and Edinburgh in the development of tools for the simulation of nanoscale silicon chip devices (transistors) and their circuit behaviour. In particular StatDes will translate and adapt world leading statistical compact model and circuit simulation and verification technology, methodology and tools. These were developed in the framework of a £4.5M EPSRC eScience Pilot Project “Meeting the design challenges of nano CMOS electronics (NanoCMOS)”, in which the Universities of Glasgow and Edinburgh are key partners. The capabilities of the tools and the knowledge generated will be exchanged with the major design and semiconductor houses and Small and Medium Enterprises (SMEs) in Scotland. The objectives are: 

  • TestCCT.pngTo deliver capabilities that will allow designers to develop products faster and more reliably in advanced nanoscale technologies without the normal, expensive “trial and error” process.
  • To translate and adapt methodology and tools that guarantee high yield and reliability and reduce the power consumption of future analogue, digital and mixed signal consumer products. These will substantially “de-risk” complex and expensive System-On-Chip (SoC) design.
  • To complement this with education training and activities that will highlight the benefits of the new capabilities and will train the designers in their use.
  • To produce case studies that will help encourage SMEs to start using the translated technology in product development. These will highlight how the toolset can be used and the likely benefits for product development from using the tools.
  • For the participating universities to learn about relevant industrial practices and technology bottlenecks. This will provide a new conduit from the universities? curiosity-driven research and generation of novel ideas to applications.

As a result the participating Scottish Universities and companies will be placed at the forefront of developments in semiconductor design and development tools.


Project Leaders

 Professor A. Asenov - Chairman and PI 

Professor A. Murray 

Advisory Board (Steering Group)

 D. Boyd (NMI) - Chairman
K. McDonald (SFC represntative)
S. Wilson (Scottish Enterprise)
J. Pennock (Wolfson)
A. Colquhoun (SELEX Galilieo)
S. East (ST)
D. Beattie (Freescale)

G. McKinnon (Cadence)

Dr. Fikru Adamu-Lema (Project Coordinator)

Core Industrial and Academic Partners

GSS-Logo.png  IBM_Logo.jpg



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