EPSRC Platform Grant

More-Moore, More than Moore and Post Moore simulations at Glasgow

The Device Modelling Group at the University of Glasgow, which has pioneered the simulation of atomic scale variability in nano CMOS transistors, has received a £1.2M boost from the Engineering and Physical Science Research Council (EPSRC) in the UK.

The aim of the new Platform Grant is to enable new strategic simulation and modelling research in the forthcoming nano-CMOS era. It will facilitate the development of the next generation of models and simulation tools targeted at the future nano-CMOS devices with molecular dimensions, unconventional new gate dielectrics and channel materials, and variable strain. It will also help to bridge the gap between the simulation techniques currently used to analyse CMOS circuits and the atomic scale techniques needed for the simulation of molecular and bioelectronic devices - allowing coherent and integrated simulation of nano-CMOS, novel nanoelectronic and nano-bio-electronic devices which are at the heart of the More-Moore, More than Moore and Post Moore future scenarios.

Fig. 1 Real 4nm channel length MOSFET (NEC) compared to ion channel and CNT. A Photoshop impression for the atomic structure of the transistor is also given.	Fig. 2 Simulated and measured (Fujitsu) variations in the electron concentration in a 35 nm MOSFET.	Fig. 3 Cartoon illustrating the integration between a MOSFET and an ion channel.

The International Technology Roadmap for Semiconductors (ITRS) stipulates that CMOS devices will cross the 10 nm barrier in 2015, with 6 nm transistors expected to be in mass production by 2020. This is not wishful thinking. As illustrated in Fig. 1 a working transistor with sub 5 nm channel demonstrated by NEC in 2003 is at the same scale as an ion channel (one of the most important types of proteins in living organisms), and carbon nanotube (posited as a possible MOSFET replacement). The main problem for the design and integration of such devices is the atomic scale variability illustrated in Fig. 2

There is a consensus that at present there is no alternative to Si based CMOS. Any nano-electronic device based on nanowires, nanodots, molecules, fullerenes, carbon sheets, etc., will have little chance of penetrating the market initially unless co-integrated with Si. As with nano-CMOS transistors, quantum effects and scattering will dominate the transport of any alternative nanoelectronic devices. Perhaps the most significant developments in the next 10-20 years will happen at the molecular and the bio/solid-state electronics interface illustrated in Fig. 3. The integration of biological materials with solid-state electronics is a novel and proliferate field in which the platform grant will allow us to maintain a position at the forefront. Thus, we advocate development and use of unified simulation techniques to describe the transport, quantum effects and scattering in a uniform way, because they will be of great demand.

“The modelling capabilities of the GDMG will help to bridge the technology-design gap for both university based and commercial UK systems design at a time of enormous, rapid technology change, and the challenges associated with the ever increasing device variability. Beneficiaries of our research and next generation simulation tools also include multinational semiconductor manufacturers and vendors of simulation software, many of which already sponsor the modelling and simulation research at Glasgow” says Professor Asen Asenov, the Principal Investigator of the Platform Grant and Leader of the Device Modelling Group.