IBM SUR Grant

The Project

The International Technology Roadmap for Semiconductors forecasts that semiconductor devices will reach decanano dimensions in the first decade of the new millennium. At the same time, doubts have been expressed by leading IC manufacturers, such as Intel, that conventional device architectures can be scaled to deep decanano dimensions and that Moore's Law can be maintained. It becomes extremely important to examine - by means of predictive device modelling and simulation - possible scaling scenarios, pitfalls, and promising decanano device architectures in order to give direction to the urgently needed, and very costly, technology developments of the next decade, and thus save unnecessary effort and expense.

A fact not yet widely realised is that the scaling of devices in integrated circuits are reaching the stage where the granularity of the electric charge and the atomicity of matter begin to introduce substantial variation in individual device characteristics. The variations in dopant position and numbers, oxide thickness pattern, gate material and geometry will introduce large 'intrinsic' fluctuations in the device characteristics and will have a crucial impact on the functionality, yield and reliability of the corresponding circuits and systems.

Due to acceleration in the Roadmap the evaluation of the impact of these effects on the next generation devices and systems must be done in haste, without waiting for the development of adequate general purpose, user friendly and efficient simulation tools. In many cases the need for rapid results may not allow algorithms to be refined and optimised, exacerbating the need for excessive computational resources.

The aims of this project are to develop simulation tools which are adequate for physical simulation of intrinsic parameter fluctuations in decanano devices and to use them on a massive scale to study the impact of the fluctuations on scaling limits, device architecture and circuit performance.

Atomistic MOSFET MOSFET with LER

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