Project Review Meeting

There will be a project review meeting on 22nd October 2007 at University College London. Details of venue and programme are available here.


Project Overview

The further CMOS scaling to sub 10nm scale creates new materials challenges for which the modelling of materials, interfaces, dopants, and defects will play key roles in process design and device performance enhancement. Intrinsic parameter fluctuations will be a major factor limiting the scaling and integration of such devices.

This consortium will bridge the gap between materials modelling and the framework of electrical device simulation. We will develop tools and approaches to simulate materials, interfaces and defects, which determine the performance of nano-CMOS devices and will connect them to appropriate device simulators. We will combine (1) atomistic and electronic structure calculations of device materials, with (2) the studies of the transport properties of devices based on the Non-equilibrium Green's Function (NEGF) techniques, and (3) with full 3D statistical device simulations.

We will then investigate, using simulations, the origins and magnitudes of intrinsic parameter fluctuations introduced by new materials like high-k dielectrics, SiGe and pure Ge in non-conventional nano-CMOS devices with sub 10 nm dimensions, including thin body silicon on insulator (SOI), planar and vertical multigate transistors. We plan to understand the importance of each individual source of intrinsic parameter fluctuations and their combined effect and to assess and compare ways to enhance fluctuation resistance in nano-CMOS transistors.
PhotoshopTM impression of a 4 nm double gate MOSFET constructed from TEM images of Si-SiO2 and PolySi-SiO2 interfaces. Simulations of a 4 nm double gate MOSFET. Potential distribution. The potential fluctuations introduced by discrete dopants are visible. Evolution of DOS from Si to SiO2 after J. Neatona and D. Muller.

Aims and objectives:

  • To link the first principle simulations, which describe the atomic and electronic structure of the sources of fluctuations including discrete dopants, localised defects, interface roughness, body thickness, composition, strain and structure variation with hierarchical device simulations. To validate the various levels of multi-scale modelling by reference to experimental data appropriate to the scale of the modelling.

  • To develop a methodology for transferring results from the costly but accurate 3D atomistic device simulations into compact statistical models and to develop their use in circuit simulations, which links the stochastic behaviour (determined by their unique atomic structure) of nano-CMOS components to the functionality of analogue, and digital circuit components.

  • To investigate, using simulations, the origins and magnitudes of intrinsic parameter fluctuations associated with the introduction of new materials like high-k dielectrics, SiGe and pure Ge in non-conventional nano-CMOS devices with sub 10 nm dimensions. We aim to understand the importance of each individual source of intrinsic parameter fluctuations and their combined effect.

  • To assess and compare ways to enhance fluctuation resistance in nano-CMOS transistors including atomic-precision dopant placement and crystalline gate dielectrics.